introduce clock_* and reset_* types

[taichi-ishitani]

Migration guide

Change type of clock and reset variables from logic to clock / reset.

• From

module ModuleA (
    i_clk: input logic,
    i_rst: input logic,
) {}

• To

module ModuleA (
    i_clk: input clock,
    i_rst: input reset,
) {}

Description

refs #622

This PR is to introduce special types below instead of posedge, negedge, async_high, async_low, sync_high and sync_low keywords.

• clock
  • clock type of which polarity is specified by the build option
• clock_posedge
  • clock type of which polarity is positive
• clock_negedge
  • clock type of which polarity is negative
• reset
  • reset type of which polarity and synchronicity are specified by the build option
• reset_async_high
  • async/high active reset type
• reset_async_low
  • async/low active reset type
• reset_sync_high
  • sync/active high reset type
• reset_sync_low
  • sync/active low reset type

The clock/reset type cast and port connection type check features (refs: #622 (comment)) are not implemented yet because the expression resolver is needed to implement these features.

[dalance]

Looks good!
I'll merge this PR and close #622.
Please open an issue for the remaining features like connection check.