Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

optimization on matrix-matrix mulitplication #172

Open
wants to merge 30 commits into
base: master
Choose a base branch
from

Conversation

Fritzkefit
Copy link

Introduces a BLIS-like approach: a macro-kernel iterates over blocks (of sizes dependent on cache-sizes and available threads) of the matrices being multiplied and a micro-kernel executes the actual multiplication. Two micro-kernels -one using the AVX instruction set, the other using the SSE instruction set- are included.

Fritzkefit and others added 30 commits September 4, 2015 22:50
…case in packing.hpp, mat-mat-mul seems to work now
… added a framework for reading cache sizes, used to calculate block sizes (not yet implemented).
…loads/stores, further bug fixes

Renamed "get_cache_sizes.hpp" to "get_block_sizes.hpp", where get_block_sizes() is called evertime prod() is invoked, since we have to dynamically assign mr/nr as they depend on wether float or double entries are processed.
The AVX-microkernels work for doubles and float, where the approach taken for float entries differs from that for doubles due to limitations of the AVX-instructions.
…pp), made sure standard-microkernel is working
… accordingly, unfortunately fails due to segfaults on amd-systems, intel-systems untested
The inline assembler in get_cache_sizes() gets a pointer to an array which should be stored in %rdi.
This was the only way I could get it to work propperly, as specifying input/output operands would yield segfaults.
Therefore, the inline assembler is in a seperate function and relies on the standard register or first function argument (i.e. %rdi).
I do not know if this could cause problems on other systems => needs to be tested.
…thouroughly tested

CPUID info can be obtained through cpuid-leaf2 or cpuid-leaf4 on intel CPUs.
It depends on the CPU, which leaf to use. Both have been implemented and
leaf2 works correctly on a core 2 quad q9400. Further,thorough testing and double checking of the huge switch-case for leaf2 has NOT been done.
quick tests did not show any performance impacts
Please enter the commit message for your changes. Lines starting
… of available threads

Please enter the commit message for your changes. Lines starting
…emory_create() etc., fixed underflows when calculatiting num_of_blocks.. and num_residue_slivers..
…ned L1/2/3_AVX/SSE_DENOMs to quickly change what fraction of cache should be filled with the blocks
@karlrupp
Copy link
Collaborator

karlrupp commented Dec 7, 2015

Thanks, @Fritzkefit ! For documentation purposes: In a face-to-face discussion we agreed that I'll take care of resolving the merge conflicts.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

2 participants