8-Bit-5-Stage-Microprocessor-Design

CURRENT STATUS : stable

Basic features

Five stage (8 bit) pipelined processor with a unique data path and a control unit.
The stages included Instruction Fetch, Instruction Decode, Instruction Execute, Memory and Write Back.
It has 17 instructions which can perform operations on operands in Registers/Immediate.
Handles Jump operations based on the status/overflow flags.
The Architecture has 16-bit address bus and can handle a total memory space of 64KB. Allocated 32KB for ROM & 32KB for RAM.
The User program is stored in ROM and fetched by the processor.
Designed an assembler which can convert the Assembly language program into machine level language.
Designed a Memory-controller for effectively mapping data space.
Designed 32KB RAM & ROM modules.
Performed simulation based verification in system Verilog where the simulator reads the assembly program from .txt file and converts into Hex code and stores in ROM

Design

Architecture

Instruction Format

Opcodes

Getting Started

Download all the project files into your local system.

Prerequisites

Mentor Questasim\Modelsim

Project Status/TODO

Compiles
Simulated all instructions

Project Setup

This project has been developed with Mentor Questasim.

Authors

Vinod Sake - Github

License

This project is licensed under the open-source license

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
work		work
8-bit Microprocessor.cr.mti		8-bit Microprocessor.cr.mti
8-bit Microprocessor.mpf		8-bit Microprocessor.mpf
8-bit microprocessor.pdf		8-bit microprocessor.pdf
ALU.sv		ALU.sv
ALU.sv.bak		ALU.sv.bak
README.md		README.md
Thumbs.db		Thumbs.db
address_multiplexer.sv		address_multiplexer.sv
address_multiplexer.sv.bak		address_multiplexer.sv.bak
address_multiplexer.vcd		address_multiplexer.vcd
address_multiplexer_tb.sv		address_multiplexer_tb.sv
address_multiplexer_tb.sv.bak		address_multiplexer_tb.sv.bak
alu.vcd		alu.vcd
alu_latch.sv		alu_latch.sv
alu_latch.sv.bak		alu_latch.sv.bak
alu_latch.vcd		alu_latch.vcd
alu_latch_tb.sv		alu_latch_tb.sv
alu_latch_tb.sv.bak		alu_latch_tb.sv.bak
alu_tb.sv		alu_tb.sv
alu_tb.sv.bak		alu_tb.sv.bak
architecture.png		architecture.png
constants.sv		constants.sv
constants.sv.bak		constants.sv.bak
control_signal_translator.sv		control_signal_translator.sv
control_signal_translator.sv.bak		control_signal_translator.sv.bak
control_signal_translator_tb.sv		control_signal_translator_tb.sv
control_signal_translator_tb.sv.bak		control_signal_translator_tb.sv.bak
control_state_machine.sv		control_state_machine.sv
control_state_machine.sv.bak		control_state_machine.sv.bak
control_state_machine.vcd		control_state_machine.vcd
control_state_machine_instruction_input.txt		control_state_machine_instruction_input.txt
control_state_machine_tb.sv		control_state_machine_tb.sv
control_state_machine_tb.sv.bak		control_state_machine_tb.sv.bak
cpu.sv		cpu.sv
cpu.sv.bak		cpu.sv.bak
cpu.txt		cpu.txt
cpu.vcd		cpu.vcd
cpu_add.txt		cpu_add.txt
cpu_mul.txt		cpu_mul.txt
cpu_program.txt		cpu_program.txt
cpu_sub.txt		cpu_sub.txt
cpu_tb.sv		cpu_tb.sv
cpu_tb.sv.bak		cpu_tb.sv.bak
datapath.sv		datapath.sv
datapath.sv.bak		datapath.sv.bak
datapath.vcd		datapath.vcd
datapath_tb.sv		datapath_tb.sv
datapath_tb.sv.bak		datapath_tb.sv.bak
external_data_bus.txt		external_data_bus.txt
generalpurpose_registers.sv		generalpurpose_registers.sv
generalpurpose_registers.sv.bak		generalpurpose_registers.sv.bak
internal_data_bus.txt		internal_data_bus.txt
jump_register.sv.bak		jump_register.sv.bak
memory_io.sv		memory_io.sv
memory_io.sv.bak		memory_io.sv.bak
memory_io_tb.sv		memory_io_tb.sv
memory_io_tb.sv.bak		memory_io_tb.sv.bak
memory_io_testing.sv		memory_io_testing.sv
memory_io_testing.sv.bak		memory_io_testing.sv.bak
mux.sv		mux.sv
mux.sv.bak		mux.sv.bak
program_counter.sv		program_counter.sv
program_counter.sv.bak		program_counter.sv.bak
program_counter.vcd		program_counter.vcd
program_counter_tb.sv		program_counter_tb.sv
program_counter_tb.sv.bak		program_counter_tb.sv.bak
ram.sv		ram.sv
ram.sv.bak		ram.sv.bak
ram.vcd		ram.vcd
ram_tb.sv		ram_tb.sv
ram_tb.sv.bak		ram_tb.sv.bak
read_cpu_ram.txt		read_cpu_ram.txt
read_cpu_rom.txt		read_cpu_rom.txt
read_ram.txt		read_ram.txt
read_rom.txt		read_rom.txt
register_16bit.sv		register_16bit.sv
register_16bit.sv.bak		register_16bit.sv.bak
register_16bit.vcd		register_16bit.vcd
register_16bit_tb.sv		register_16bit_tb.sv
register_16bit_tb.sv.bak		register_16bit_tb.sv.bak
rom.sv		rom.sv
rom.sv.bak		rom.sv.bak
rom_tb.sv		rom_tb.sv
rom_tb.sv.bak		rom_tb.sv.bak
tes.sv.bak		tes.sv.bak
test.cr.mti		test.cr.mti
test.mpf		test.mpf
test.sv.bak		test.sv.bak
vsim.wlf		vsim.wlf
write_rom.txt		write_rom.txt

vinodsake/8-Bit-5-Stage-Microprocessor-Design

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