Update theory.rst

docs/theory.rst

@@ -163,7 +163,7 @@ To do so, we apply a `Kronecker product <https://en.wikipedia.org/wiki/Kronecker
 
 The operation in :eq:`x_3bit` swaps the amplitudes of 0 and 1 for the first bit out of three, but leaves the second and third bits alone.  Using the identity matrix :math:`I` preserves the amplitudes of the :math:`x_{0nn}` and :math:`x_{1nn}` positions.  The expanded matrix in :eq:`x_3bit_3` now has the proper dimensionality to be multiplied directly against the amplitude vector.
 
-.. note:: It's important to remember here that, unlike a classical :math:`NOT` which directly inverts a bit, the :math:`X` gate swaps the *amplitudes* for the states where the qubit is 1 with the amplitudes where the qubit is 0. If the value of :math:`M[0]` is :math:`\lvert100\rangle`, then a subsequent :math:`X[0]` gate would exchange :math:`x_{100}`and :math:`x_{000}` and therefore leave the state as :math:`\lvert000\rangle`.  See `Quantum Logic Gates <https://en.wikipedia.org/wiki/Quantum_logic_gate#Circuit_composition_and_entangled_states>`_ for more information.
+.. note:: It's important to remember here that, unlike a classical :math:`NOT` which directly inverts a bit, the :math:`X` gate swaps the *amplitudes* for the states where the qubit is 1 with the amplitudes where the qubit is 0. If the value of :math:`M[0]` is :math:`\lvert100\rangle`, then a subsequent :math:`X[0]` gate would exchange :math:`x_{100}` and :math:`x_{000}` and therefore leave the state as :math:`\lvert000\rangle`.  See `Quantum Logic Gates <https://en.wikipedia.org/wiki/Quantum_logic_gate#Circuit_composition_and_entangled_states>`_ for more information.
 
 Implementing this naively would require matrices sized at :math:`2^{2N}` complex numbers for :math:`N` bits (as illustrated above in :eq:`x_3bit_3`).  This rapidly grows prohibitive in memory usage, and this is the primary limitation for simulating quantum systems using classical components.  Fortunately, these types of matrix operations are easily optimized for both memory usage and parallelization.