[hal/gd32h7xx] update

source/hal/driver/GigaDevice/GD32H7XX/GD32H759/startup_gd32h759.c

@@ -549,10 +549,8 @@ void Reset_Handler(void)
     vsf_arch_set_stack((uintptr_t)&__INITIAL_SP);
     vsf_hal_pre_startup_init();
 
-    //! enable FPU
-    SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));  /* set CP10 and CP11 Full Access */
-
-    SCB->VTOR = (uint32_t)__VECTOR_TABLE;
-
+    SystemInit();
+    SCB_EnableICache();
+    SCB_EnableDCache();
     __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
 }

source/hal/driver/GigaDevice/GD32H7XX/common/common.c

@@ -29,3 +29,11 @@
 /*============================ IMPLEMENTATION ================================*/
 
 #include "hal/driver/common/swi/arm/vsf_swi_template.inc"
+
+// this function should be in gd32h7xx_misc.c, but this file is not included.
+//  So implement this function here.
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
+{
+    SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
+    __DSB();
+}

source/hal/driver/GigaDevice/GD32H7XX/common/vendor/Include/gd32h7xx.h

@@ -350,7 +350,7 @@ typedef enum IRQn {
 
 /* includes */
 #include "core_cm7.h"
-//#include "system_gd32h7xx.h"
+#include "system_gd32h7xx.h"
 #include <stdint.h>
 
 /* enum definitions */

source/hal/driver/GigaDevice/GD32H7XX/common/vendor/Include/system_gd32h7xx.h

@@ -0,0 +1,50 @@
+/*!
+    \file  system_gd32h7xx.h
+    \brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File for
+           gd32h7xx Device Series
+*/
+
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2024, GigaDevice Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32H7XX_H
+#define SYSTEM_GD32H7XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit (void);
+/* update the SystemCoreClock with current core clock retrieved from cpu registers */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32H7XX_H */