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drm/i915: Unify intel_pipe_has_type() and intel_pipe_will_have_type()
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With the introduction of the output_types mask, intel_pipe_has_type()
and intel_pipe_will_have_type() are basically the same thing. Replace
them with a new intel_crtc_has_type() (identical to
intel_pipe_will_have_type() actually).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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@vsyrjala
vsyrjala committed Dec 21, 2015
1 parent 571aa46 commit 556ee4e
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Showing 3 changed files with 48 additions and 59 deletions.
18 changes: 9 additions & 9 deletions drivers/gpu/drm/i915/intel_audio.c
View file
Expand Up @@ -154,7 +154,7 @@ static bool audio_rate_need_prog(struct intel_crtc *crtc,
{
if (((mode->clock == TMDS_297M) ||
(mode->clock == TMDS_296M)) &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
return true;
else
return false;
Expand Down Expand Up @@ -262,8 +262,8 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder)
tmp |= AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DISPLAYPORT) ||
intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
I915_WRITE(HSW_AUD_CFG(pipe), tmp);

Expand Down Expand Up @@ -329,7 +329,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
tmp = I915_READ(HSW_AUD_CFG(pipe));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DISPLAYPORT))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
Expand Down Expand Up @@ -390,7 +390,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
tmp |= AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DISPLAYPORT))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
I915_WRITE(aud_config, tmp);

Expand Down Expand Up @@ -476,8 +476,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DISPLAYPORT) ||
intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
Expand Down Expand Up @@ -515,8 +515,8 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)

/* ELD Conn_Type */
connector->eld[5] &= ~(3 << 2);
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_DP_MST))
if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DISPLAYPORT) ||
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP_MST))
connector->eld[5] |= (1 << 2);

connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
Expand Down
86 changes: 37 additions & 49 deletions drivers/gpu/drm/i915/intel_display.c
View file
Expand Up @@ -506,22 +506,9 @@ needs_modeset(struct drm_crtc_state *state)
return drm_atomic_crtc_needs_modeset(state);
}

/**
* Returns whether any output on the specified pipe is of the specified type
*/
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
{
return crtc->config->output_types & (1 << type);
}

/**
* Returns whether any output on the specified pipe will have the specified
* type after a staged modeset is complete, i.e., the same as
* intel_pipe_has_type() but looking at encoder->new_crtc instead of
* encoder->crtc.
*/
static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
enum intel_output_type type)
/* Returns whether any output on the specified pipe is of the specified type */
bool intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
enum intel_output_type type)
{
return crtc_state->output_types & (1 << type);
}
Expand All @@ -532,7 +519,7 @@ intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
struct drm_device *dev = crtc_state->base.crtc->dev;
const intel_limit_t *limit;

if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_is_dual_link_lvds(dev)) {
if (refclk == 100000)
limit = &intel_limits_ironlake_dual_lvds_100m;
Expand All @@ -556,15 +543,15 @@ intel_g4x_limit(struct intel_crtc_state *crtc_state)
struct drm_device *dev = crtc_state->base.crtc->dev;
const intel_limit_t *limit;

if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_is_dual_link_lvds(dev))
limit = &intel_limits_g4x_dual_channel_lvds;
else
limit = &intel_limits_g4x_single_channel_lvds;
} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
limit = &intel_limits_g4x_hdmi;
} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
limit = &intel_limits_g4x_sdvo;
} else /* The option is for other outputs */
limit = &intel_limits_i9xx_sdvo;
Expand All @@ -585,7 +572,7 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
else if (IS_G4X(dev)) {
limit = intel_g4x_limit(crtc_state);
} else if (IS_PINEVIEW(dev)) {
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
limit = &intel_limits_pineview_lvds;
else
limit = &intel_limits_pineview_sdvo;
Expand All @@ -594,14 +581,14 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
} else if (IS_VALLEYVIEW(dev)) {
limit = &intel_limits_vlv;
} else if (!IS_GEN2(dev)) {
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
limit = &intel_limits_i9xx_lvds;
else
limit = &intel_limits_i9xx_sdvo;
} else {
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
limit = &intel_limits_i8xx_lvds;
else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
limit = &intel_limits_i8xx_dvo;
else
limit = &intel_limits_i8xx_dac;
Expand Down Expand Up @@ -721,7 +708,7 @@ i9xx_select_p2_div(const intel_limit_t *limit,
{
struct drm_device *dev = crtc_state->base.crtc->dev;

if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
/*
* For LVDS just rely on its current settings for dual-channel.
* We haven't figured out how to reliably set up different
Expand Down Expand Up @@ -1650,9 +1637,10 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
struct intel_crtc *crtc;
int count = 0;

for_each_intel_crtc(dev, crtc)
for_each_intel_crtc(dev, crtc) {
count += crtc->base.state->active &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
}

return count;
}
Expand Down Expand Up @@ -1740,7 +1728,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)

/* Disable DVO 2x clock on both PLLs if necessary */
if (IS_I830(dev) &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
!intel_num_dvo_pipes(dev)) {
I915_WRITE(DPLL(PIPE_B),
I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
Expand Down Expand Up @@ -1969,7 +1957,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
* here for both 8bpc and 12bpc.
*/
val &= ~PIPECONF_BPC_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
val |= PIPECONF_8BPC;
else
val |= pipeconf_val & PIPECONF_BPC_MASK;
Expand All @@ -1978,7 +1966,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
val &= ~TRANS_INTERLACE_MASK;
if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
if (HAS_PCH_IBX(dev_priv->dev) &&
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
val |= TRANS_LEGACY_INTERLACED_ILK;
else
val |= TRANS_INTERLACED;
Expand Down Expand Up @@ -6705,7 +6693,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
* - LVDS dual channel mode
* - Double wide pipe
*/
if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
pipe_config->pipe_src_w &= ~1;

Expand Down Expand Up @@ -7175,7 +7163,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,

if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
refclk = 100000;
} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
refclk = dev_priv->vbt.lvds_ssc_freq;
DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Expand Down Expand Up @@ -7218,7 +7206,7 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
crtc_state->dpll_hw_state.fp0 = fp;

crtc->lowfreq_avail = false;
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
reduced_clock) {
crtc_state->dpll_hw_state.fp1 = fp2;
crtc->lowfreq_avail = true;
Expand Down Expand Up @@ -7405,8 +7393,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,

/* Set HBR and RBR LPF coefficients */
if (pipe_config->port_clock == 162000 ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
0x009f0003);
else
Expand All @@ -7433,8 +7421,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,

coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DISPLAYPORT) ||
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_EDP))
coreclk |= 0x01000000;
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);

Expand Down Expand Up @@ -7620,12 +7608,12 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,

i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);

is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
is_sdvo = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);

dpll = DPLL_VGA_MODE_DIS;

if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
dpll |= DPLLB_MODE_LVDS;
else
dpll |= DPLLB_MODE_DAC_SERIAL;
Expand Down Expand Up @@ -7668,7 +7656,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,

if (crtc_state->sdvo_tv_clock)
dpll |= PLL_REF_INPUT_TVCLKINBC;
else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
intel_panel_use_ssc(dev_priv) && num_connectors < 2)
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
else
Expand Down Expand Up @@ -7698,7 +7686,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,

dpll = DPLL_VGA_MODE_DIS;

if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
} else {
if (clock->p1 == 2)
Expand All @@ -7709,10 +7697,10 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
dpll |= PLL_P2_DIVIDE_BY_4;
}

if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
dpll |= DPLL_DVO_2X_MODE;

if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
intel_panel_use_ssc(dev_priv) && num_connectors < 2)
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
else
Expand Down Expand Up @@ -7742,7 +7730,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
crtc_vtotal -= 1;
crtc_vblank_end -= 1;

if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
else
vsyncshift = adjusted_mode->crtc_hsync_start -
Expand Down Expand Up @@ -7905,7 +7893,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)

if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
if (INTEL_INFO(dev)->gen < 4 ||
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
else
pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
Expand Down Expand Up @@ -9001,7 +8989,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));

is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
is_lvds = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS);

WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
Expand Down Expand Up @@ -13048,7 +13036,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)

crtc->scanline_offset = vtotal - 1;
} else if (HAS_DDI(dev) &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
crtc->scanline_offset = 2;
} else
crtc->scanline_offset = 1;
Expand Down
3 changes: 2 additions & 1 deletion drivers/gpu/drm/i915/intel_drv.h
View file
Expand Up @@ -1079,7 +1079,8 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
struct drm_file *file_priv);
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe);
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
bool intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
enum intel_output_type type);
static inline void
intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
Expand Down

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