mips-cpu

Verilog implementation of a MIPS-R2000 CPU, based on the concept in this book

Currently supported instructions:

lw sw lui

add addu addiu

sub subu

and or ori

beq bne j

sll srl

slt slti

Name		Name	Last commit message	Last commit date
Latest commit History 91 Commits
others		others
.gitignore		.gitignore
ALU.v		ALU.v
ConditionCheck.v		ConditionCheck.v
Control.v		Control.v
DataMemory.v		DataMemory.v
EXMEMReg.v		EXMEMReg.v
Extender.v		Extender.v
ForwardingUnit.v		ForwardingUnit.v
GPR.v		GPR.v
HazardUnit.v		HazardUnit.v
IDEXReg.v		IDEXReg.v
IFIDReg.v		IFIDReg.v
InstructionMemory.v		InstructionMemory.v
LICENSE		LICENSE
MEMWBReg.v		MEMWBReg.v
MIPS_R2000.v		MIPS_R2000.v
MIPS_R2000_tb.v		MIPS_R2000_tb.v
Makefile		Makefile
PCU.v		PCU.v
README.md		README.md
clk_div.v		clk_div.v
icf.xdc		icf.xdc
instruction_def.v		instruction_def.v
seg7x16.v		seg7x16.v
signal_def.v		signal_def.v