MIPS32

A pipelined implementation of MIPS32 processor using Verilog HDL

MIPS32 is a Reduced Instruction Set Computer (RISC) architecture, and here, this particular processor is designed in Verilog HDL with 5 phases of pipeline, namely Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), Write Back (WB). This design has a small subset of the instructions (and some simplifying assumptions), and verification of the design is done using some testbench and GTKWave simulator.