WIP

riscvmodel/golden.py

@@ -66,11 +66,9 @@ def commit(self, trace, *, insn = None):
         # Execute the expected instruction and verify the state is the same
         exp_trace = self.model.issue(exp)
         if not self.model.check(trace):
-            print(exp_trace)
             raise GoldenException("Unexpected state change: {}, expected: {}".format(",".join([str(t) for t in trace]),
                                                                                      ",".join([str(t) for t in exp_trace])))
 
-
     def reset(self, *, pc: int = 0):
         self.model.reset(pc=pc)
         self.pc = pc

riscvmodel/insn.py

@@ -4,7 +4,7 @@
 from .variant import Variant
 from .model import State
 from .types import Immediate
-
+from .variant import RV32I
 
 class Instruction(metaclass=ABCMeta):
     """
@@ -207,7 +207,7 @@ def __str__(self):
     def __eq__(self, other):
         if not super().__eq__(other):
             return False
-        return self.rd == other.rd and self.rs2 == other.rs2 and self.shamt == other.shamt
+        return self.rd == other.rd and self.rs1 == other.rs1 and self.shamt == other.shamt
 
 
 class InstructionSType(Instruction):
@@ -390,7 +390,8 @@ def __eq__(self, other):
             return False
         return self.rd == other.rd and self.imm == other.imm
 
-def isa(mnemonic: str, opcode: int, funct3: int=None, funct7: int=None):
+
+def isa(mnemonic: str, opcode: int, funct3: int=None, funct7: int=None, *, variant=RV32I, extension=None):
     """
     Decorator for the instructions. The decorator contains the static information for the instructions, in particular
     the encoding parameters and the assembler mnemonic.
@@ -409,6 +410,8 @@ class WrappedClass(wrapped):
             _opcode = opcode
             _funct3 = funct3
             _funct7 = funct7
+            _variant = variant
+            _extension = extension
 
             @staticmethod
             def _match(machinecode: int):

riscvmodel/isa.py

@@ -1,7 +1,14 @@
 from .insn import *
+from .variant import RV64I
+
 
 @isa("lui", 0x37)
 class InstructionLUI(InstructionUType):
+    """
+    The Load Upper Immediate (LUI) instruction loads the given immediate (unsigned 20 bit) to the upper 20 bit
+    of the destination register. The lower bits are set to zero in the destination register. This instruction
+    can be used to efficiently form constants, as a sequence of LUI and ORI for example.
+    """
     def execute(self, model: State):
         model.intreg[self.rd] = (self.imm << 12)
 
@@ -141,7 +148,7 @@ def execute(self, model: State):
 @isa("sltiu", 0x13, 3)
 class InstructionSLTIU(InstructionIType):
     def execute(self, model: State):
-        if model.intreg[self.rs1].unsigned() < self.imm:
+        if model.intreg[self.rs1].unsigned() < int(self.imm):
             model.intreg[self.rd] = 1
         else:
             model.intreg[self.rd] = 0
@@ -174,7 +181,7 @@ def execute(self, model: State):
 @isa("srli", 0x13, 5, 0x00)
 class InstructionSRLI(InstructionISType):
     def execute(self, model: State):
-        model.intreg[self.rd] = model.intreg[self.rs1].unsigned() >> self.shamt
+        model.intreg[self.rd] = model.intreg[self.rs1].unsigned() >> int(self.shamt)
 
 
 @isa("srai", 0x13, 5, 0x20)
@@ -198,7 +205,7 @@ def execute(self, model: State):
 @isa("sll", 0x33, 1, 0x00)
 class InstructionSLL(InstructionRType):
     def execute(self, model: State):
-        model.intreg[self.rd] = model.intreg[self.rs1] << model.intreg[self.rs2]
+        model.intreg[self.rd] = model.intreg[self.rs1] << (model.intreg[self.rs2] & 0x1f)
 
 
 @isa("slt", 0x33, 2, 0x00)
@@ -249,6 +256,71 @@ def execute(self, model: State):
         model.intreg[self.rd] = model.intreg[self.rs1] & model.intreg[self.rs2]
 
 
+@isa("fence", 0xF, 0, 0x00)
+class InstructionFENCE(Instruction):
+    pass
+
+
+@isa("fence.i", 0xF, 1, 0x00)
+class InstructionFENCEI(Instruction):
+    pass
+
+
+@isa("ecall", 0x73, 0)
+class InstructionECALL(Instruction):
+    pass
+
+
+@isa("ebreak", 0x73, 0)
+class InstructionEBREAK(Instruction):
+    pass
+
+
+@isa("csrrw", 0x73, 1)
+class InstructionCSRRW(Instruction):
+    pass
+
+
+@isa("csrrs", 0x73, 2)
+class InstructionCSRRS(Instruction):
+    pass
+
+
+@isa("csrrc", 0x73, 3)
+class InstructionCSRRC(Instruction):
+    pass
+
+
+@isa("csrrwi", 0x73, 5)
+class InstructionCSRRWI(Instruction):
+    pass
+
+
+@isa("csrrsi", 0x73, 6)
+class InstructionCSRRSI(Instruction):
+    pass
+
+
+@isa("csrrci", 0x73, 7)
+class InstructionCSRRCI(Instruction):
+    pass
+
+
+@isa("lwu", 0x3, 6, variant=RV64I)
+class InstructionLWU(InstructionIType):
+    pass
+
+
+@isa("ld", 0x3, 3, variant=RV64I)
+class InstructionLD(InstructionIType):
+    pass
+
+
+@isa("sd", 0x23, 3, variant=RV64I)
+class InstructionSD(InstructionISType):
+    pass
+
+
 @isa_pseudo()
 class InstructionNOP(InstructionADDI):
     def __init__(self):

riscvmodel/model.py

@@ -130,7 +130,7 @@ def randomize(self):
     def reset(self, *, pc: int = 0):
         self.state.reset(pc)
 
-    def check(self, traces):
+    def check(self, traces, exp=None):
         for t in traces:
             if isinstance(t, TraceIntegerRegister):
                 if int(self.state.intreg[t.id]) != int(t.value):