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wangeddie67 edited this page Jun 3, 2020 · 25 revisions

Welcome to the ESYSim wiki!

NOTE: This user manual explains the design idea behind the code. Please check doxygen documents for details about the code.

Components

ESYSim is a tool collection for many-core system simulation. It contains:

  • ESYAlpha: many-core system simulator with cycle-accurate core model.
  • ESYMap: many-core system simulator with light-weight core model.
  • ESYNet: cycle-accurate network-on-chip simulator.
  • ESYNetRtl: RTL network-on-chip generator.
  • VisualNoC: visualization platform for network-on-chip.
  • VisualArch: visualization platform for the many-core system.

Installation

First, download the code from github. Then compile codes on your machine. ESYSim needs system environment as follow:

  • All tools only support Linux OS.
    • Linux library: dialog;
  • gcc/g++ compiler;
  • Qt5 and above;
  • python.
    • Python library: pythondialog.

The components are compiled separately. Please enter the following folder in the given order and run make command.

  • Compile ESYAlpha
cd $ESYSIM_ROOT/esyalpha
make clean
make
  • Compile ESYNet
cd $ESYSIM_ROOT/esynet
make cleanall
make esynet
  • Compile QtParallel
cd $ESYSIM_ROOT/qtparallel
qmake
make
  • Compile Qwt for visualization tools
cd $ESYSIM_ROOT/visualtool/qwt
qmake
make
  • Compile VisualNoC
cd $ESYSIM_ROOT/visualtool
qmake visualnoc.pro
make
  • Compile VisualArch
cd $ESYSIM_ROOT/visualtool
qmake visualarch.pro
make

Documents

Detail documents for all tools:

History

The whole project can trace back to 2013 when our research team got Simplescalar and Popnet.

In 2014, VisualNoC, one of the major components, was developed to debug the fault-tolerant routing algorithms. It is the first developed simulator.

By 2015, our team made many modifications on Simplescalar and Popnet. Meanwhile, we developed one simulator used to study the Mapping Algorithms. In this period, VisualNoC became mature enough after several iterations. Thus, in 2015, the ESYSim project is raised to organize all the simulator projects in our group. ESY is the Chinese pronounce of the room number of our servers. ESYSim project contains four major parts: esyalpha, esynet, esymap, and visualnoc.

In 2016, VisualNoC joined university booth in DATE2016 in Dresden, Germany, and DAC2016 in Austin, USA.

In 2017, ESYSim was extended from software to hardware as well as from NoC to Many-core system. The prototype of esynetrtl, esyarch and visualarch have been added into the project. ESYSim won Grand Price in the Integrated Circuit Design Contest in the Chinese Graduate Electronic Design Contest, which is the predecessors of Integrated Circuit Design Context in CPIPC.

Acknowledgement

At first, to response the intellectual property, we would like to thank the developers of SimpleScalar and Popnet, which is the foundation of ESYSim. We also thanks open-source project TinyXML and Qwt, which is also used in ESYSim.

We want to thank our former members who have contributed their intelligent, creativity and hard work to this project. In the order of their graduations: Hui Dong (2012), Tingbin Chu (2012), Xiaofan Zhang (2013), Yang Huang (2014), Xinxin Lin (2014). We wish them an excellent career and a beautiful life.

We would like to thank Dr. Huang from UESTC, China. The project would not be existed without his support. It is not common to support a project which is mainly focused on developing a simulator.

We also would like to thank Prof. Axel Jantsch from TU Wien and Prof. Masoumeh Ebrahimi from KTH. They have given us valuable suggestions to develop the simulators.

Copyright @ Junshi Wang

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