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*.mac: ssr->mmr rename
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@wfjm
wfjm committed Aug 9, 2022
1 parent e8fc9fa commit fc10cc5
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16 changes: 8 additions & 8 deletions tools/asm-11/lib/defs_mmu.mac
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@@ -1,13 +1,13 @@
; $Id: defs_mmu.mac 1261 2022-07-23 16:15:03Z mueller $
; $Id: defs_mmu.mac 1272 2022-08-07 17:37:51Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; definitions for mmu registers (as in defs_mmu.das)
;
ssr0 = 177572
ssr1 = 177574
ssr2 = 177576
ssr3 = 172516
mmr0 = 177572
mmr1 = 177574
mmr2 = 177576
mmr3 = 172516
;
uipdr = 177600 ; usr i page dsc base
udpdr = 177620 ; usr d page dsc base
Expand All @@ -22,7 +22,7 @@
kipar = 172340 ; ker i page addr base
kdpar = 172360 ; ker d page addr base
;
; symbol definitions for ssr0
; symbol definitions for mmr0
;
m0.anr = 100000 ; abort non-resident
m0.ale = 040000 ; abort segment length
Expand All @@ -34,7 +34,7 @@
m0.dsp = 000020 ; enable i/d space
m0.ena = 000001 ; enable mmu
;
; symbol definitions for ssr3
; symbol definitions for mmr3
;
m3.eub = 000040 ; enable unibus map
m3.e22 = 000020 ; enable 22bit addressing
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11 changes: 6 additions & 5 deletions tools/tbench/w11a/test_w11a_cpuerr.tcl
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@@ -1,9 +1,10 @@
# $Id: test_w11a_cpuerr.tcl 1254 2022-07-13 06:16:19Z mueller $
# $Id: test_w11a_cpuerr.tcl 1272 2022-08-07 17:37:51Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2016-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-06 1272 1.0.1 ssr->mmr rename
# 2016-12-27 831 1.0 Initial version
#
# Test cpuerr register
Expand Down Expand Up @@ -57,15 +58,15 @@ t.002:
;
jsr pc, mminki ; init MMU, kernel I space only
mov #177400,@#kipar+014 ; kipar(6): to page below I/O page
mov #m3.e22,@#ssr3 ; enable 22bit
mov #m0.ena,@#ssr0 ; enable MMU
mov #m3.e22,@#mmr3 ; enable 22bit
mov #m0.ena,@#mmr0 ; enable MMU
;
mov #t.004,r4 ; setup continuation address
mov #140000,r0 ; r0 points to non-existent memory
tst (r0) ; access
; !! will trap to 004 and set 000040 !!
halt ; blocker
t.004: clr @#ssr0 ; disable MMU
t.004: clr @#mmr0 ; disable MMU
;
; test 005: I/O bus timeout abort; will set bit cp.ito -----------------------
;
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27 changes: 14 additions & 13 deletions tools/tbench/w11a_cmon/test_cmon_logs.tcl
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@@ -1,9 +1,10 @@
# $Id: test_cmon_logs.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_cmon_logs.tcl 1272 2022-08-07 17:37:51Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-06 1272 2.0.1 ssr->mmr rename
# 2017-04-23 885 2.0 adopt to revised interface
# 2015-08-02 707 1.0 Initial version
#
Expand Down Expand Up @@ -578,19 +579,19 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
mov #<77400+md.arw>,@#<kipdr+16> ; s7: slf=127; ed=0; acf=rw
mov #177600,@#<kipar+16> ; to io page (22 bit)
mov #234,vtst
mov #m3.e22,@#ssr3 ; enable 22bit mode
mov #<m0.ent+m0.ena>,@#ssr0 ; enable mmu, enable traps
mov #m3.e22,@#mmr3 ; enable 22bit mode
mov #<m0.ent+m0.ena>,@#mmr0 ; enable mmu, enable traps
;
mov vtst,r0 ; no trap (is read)
inc r0
mov r0,vtst ; should trap (is write)
inc vtst ; should trap (is read-mod-write)
;
clr @#ssr0
clr @#mmr0
halt
stop:
;
vh.mmu: mov #<m0.ent+m0.ena>,@#ssr0 ; clear error flags, keep enables
vh.mmu: mov #<m0.ent+m0.ena>,@#mmr0 ; clear error flags, keep enables
rti
;
vh.xxx: halt
Expand Down Expand Up @@ -776,8 +777,8 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
mov #077400,@#<kipdr+02> ; s1: slf=127; ed=0; acf=abo
mov #<77400+md.arw>,@#<kipdr+16> ; s7: slf=127; ed=0; acf=rw
mov #177600,@#<kipar+16> ; to io page (22 bit)
mov #m3.e22,@#ssr3 ; enable 22bit mode
mov #m0.ena,@#ssr0 ; enable mmu
mov #m3.e22,@#mmr3 ; enable 22bit mode
mov #m0.ena,@#mmr0 ; enable mmu
;
mov #bad,r5 ; to blocker
mov vok,a ; should be ok
Expand All @@ -787,18 +788,18 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
ok: mov #bad,r5 ; to blocker
mov vok,a ; should be ok again
;
clr @#ssr0
clr @#mmr0
halt
stop:
bad: halt
;
a: .word 0
b: .word 0
;
vh.mmu: mov @#ssr0,r0 ; check ssr0
mov @#ssr1,r1 ; check ssr1
mov @#ssr2,r2 ; check ssr2
mov #m0.ena,@#ssr0 ; clear error flags, keep enable
vh.mmu: mov @#mmr0,r0 ; check mmr0
mov @#mmr1,r1 ; check mmr1
mov @#mmr2,r2 ; check mmr2
mov #m0.ena,@#mmr0 ; clear error flags, keep enable
mov r5,(sp) ; use recovery address
rti
;
Expand Down
91 changes: 46 additions & 45 deletions tools/tcode/cpu_mmu.mac
View file
@@ -1,17 +1,18 @@
; $Id: cpu_mmu.mac 1264 2022-07-30 07:42:17Z mueller $
; $Id: cpu_mmu.mac 1272 2022-08-07 17:37:51Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2022-08-06 1272 1.0.1 ssr->mmr rename
; 2022-07-28 1264 1.0 Initial version
; 2022-07-24 1262 0.1 First draft
;
; Test CPU MMU: all aspects of the MMU
; Section A: pdr,par registers
; Section B: ssr0,ssr3 registers, mapping, instructions
; Section C: ssr1 register and traps
; Section D: ssr2 register and aborts
; Section B: mmr0,mmr3 registers, mapping, instructions
; Section C: mmr1 register and traps
; Section D: mmr2 register and aborts
;
.include |lib/tcode_std_base.mac|
.include |lib/defs_mmu.mac|
Expand Down Expand Up @@ -156,34 +157,34 @@ ta0102:
;
9999$: iot ; end of test A1.2
;
; Section B: ssr0,ssr3 registers, mapping, instructions ======================
; Section B: mmr0,mmr3 registers, mapping, instructions ======================
; Test whether address mapping works (traps and aborts avoided)
;
; Test B1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Test ssr0, ssr3 write/read and clear by RESET
; Test mmr0, mmr3 write/read and clear by RESET
;
; This test verifies
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 000 000 000 000 101 ---- RESET (clear ssr0,ssr3)
; 0 000 000 000 000 101 ---- RESET (clear mmr0,mmr3)
;
; Test B1.1 -- test ssr0 write/read ++++++++++++++++++++++++++++++++++
; Test B1.1 -- test mmr0 write/read ++++++++++++++++++++++++++++++++++
; Test all writable bits except m0.ena
;
tb0101: mov #ssr0,r0 ; ptr to ssr0
tb0101: mov #mmr0,r0 ; ptr to mmr0
mov #m0.ico,r1 ; instruction complete flag
mov #1010$,r4 ; ptr to data
mov #1011$,r3 ; ptr to data end
100$: mov (r4),(r0) ; write ssr0
mov (r0),r5 ; read ssr0
100$: mov (r4),(r0) ; write mmr0
mov (r0),r5 ; read mmr0
bic r1,r5 ; mask instruction complete
hcmpeq r5,(r4)+ ; check
cmp r4,r3 ; more to do ?
blo 100$
;
reset ; ssr0 has 5 bits set, check clear
mov (r0),r5 ; read ssr0
reset ; mmr0 has 5 bits set, check clear
mov (r0),r5 ; read mmr0
bic r1,r5 ; mask instruction complete
htsteq r5 ; check ssr0 cleared
htsteq r5 ; check mmr0 cleared
jmp 9999$
;
1010$: .word m0.anr ; abort flags
Expand All @@ -196,19 +197,19 @@ tb0101: mov #ssr0,r0 ; ptr to ssr0
;
9999$: iot ; end of test B1.1
;
; Test B1.2 -- test ssr3 write/read ++++++++++++++++++++++++++++++++++
; Test B1.2 -- test mmr3 write/read ++++++++++++++++++++++++++++++++++
; Test all writable bits; mmu is off, and unibus map not used
;
tb0102: mov #ssr3,r0 ; ptr to ssr3
tb0102: mov #mmr3,r0 ; ptr to mmr3
mov #1010$,r4 ; ptr to data
mov #1011$,r3 ; ptr to data end
100$: mov (r4),(r0) ; write ssr3
100$: mov (r4),(r0) ; write mmr3
hcmpeq (r0),(r4)+ ; check
cmp r4,r3 ; more to do ?
blo 100$
;
reset ; ssr3 has 5 bits set, check clear
htsteq (r0) ; check ssr3 cleared
reset ; mmr3 has 5 bits set, check clear
htsteq (r0) ; check mmr3 cleared
jmp 9999$
;
1010$: .word m3.eub
Expand All @@ -227,27 +228,27 @@ tb0102: mov #ssr3,r0 ; ptr to ssr3
; Test B2.1 -- test 1-to-1 kernel mode mapping +++++++++++++++++++++++
; simply enable MMU, shouldnt make a difference
; test that 18bit mode extends I/O page addressing
; test that RESET clears ssr0 and ssr3
; test that RESET clears mmr0 and mmr3
;
tb0201: mov #123456,1000$
; enable mmu in 18bit mode
clr ssr3 ; no d dspace, no 22bit
mov #m0.ena,ssr0 ; enable mmu
hbitne #m0.ena,ssr0 ; test bit ;! MMU 18
clr mmr3 ; no d dspace, no 22bit
mov #m0.ena,mmr0 ; enable mmu
hbitne #m0.ena,mmr0 ; test bit ;! MMU 18
hcmpeq 1000$,#123456 ; check marker
; verify I/O page mapping in 18bit mode (007600 must be OK)
mov #kipar7,r0 ; ptr to kipar7
bic #170000,(r0) ; clear to 4 bits in kipar7
hcmpeq (r0),#007600 ; kipar7 still seen ???
bis #170000,(r0) ; restore kipar7
hcmpeq (r0),#177600
; enable mmu in 22bit mode; check that ssr3 still seen
mov #m3.e22,ssr3
hcmpeq ssr3,#m3.e22 ; test ssr3 stll seen ??? ;! MMU 22
; enable mmu in 22bit mode; check that mmr3 still seen
mov #m3.e22,mmr3
hcmpeq mmr3,#m3.e22 ; test mmr3 stll seen ??? ;! MMU 22
; test RESET
reset ; should clear ssr0 and ssr3
htsteq ssr0 ; check ssr0 cleared ;! MMU off
htsteq ssr3 ; check ssr3 cleared
reset ; should clear mmr0 and mmr3
htsteq mmr0 ; check mmr0 cleared ;! MMU off
htsteq mmr3 ; check mmr3 cleared
jmp 9999$
;
1000$: .word 0
Expand All @@ -265,8 +266,8 @@ tb0202: mov #kipar6,r0 ; ptr to kipar6
mov #140100,100(r5) ; init markers
clr 102(r5)
;
clr ssr3 ; no d dspace, no 22bit
mov #m0.ena,ssr0 ; enable mmu ;! MMU 18
clr mmr3 ; no d dspace, no 22bit
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
; check in 1-to-1 mapping
hcmpeq (r5),#140000
htsteq 2(r5)
Expand Down Expand Up @@ -306,8 +307,8 @@ tb0301:
mov #vhuemt,v..emt
clr v..emt+2 ; pr0 kernel
; enable mmu
clr ssr3 ; no d dspace, no 22bit
mov #m0.ena,ssr0 ; enable mmu ;! MMU 18
clr mmr3 ; no d dspace, no 22bit
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
;
; run code vc0 in user mode --------------------------------
;
Expand Down Expand Up @@ -383,8 +384,8 @@ tb0302:
mov #vhuemt,v..emt
clr v..emt+2 ; pr0 kernel
; enable mmu
mov #m3.dum,ssr3 ; user d dspace, no 22bit
mov #m0.ena,ssr0 ; enable mmu ;! MMU 18
mov #m3.dum,mmr3 ; user d dspace, no 22bit
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
;
; run code vc1 in user mode --------------------------------
;
Expand Down Expand Up @@ -526,20 +527,20 @@ tb0302:
;
9999$: iot ; end of test B3.2
;
; Section C: ssr1 register and traps =========================================
; Section C: mmr1 register and traps =========================================
;
; Test C1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Test C1.1 -- test ssr1 response via set abort in ssr0 trick ++++++++
; Test C1.1 -- test mmr1 response via set abort in mmr0 trick ++++++++
; Test method (concept seen in ekbee1)
; - start with ssr1 cleared, ssr1 will track
; - write one of the 3 abort bits in ssr1 (all three are tested)
; - that will freeze ssr1
; - start with mmr1 cleared, mmr1 will track
; - write one of the 3 abort bits in mmr1 (all three are tested)
; - that will freeze mmr1
; - the register signature of the write can be inspected
;
tc0101: mov #1000$,r1 ; ptr to abort bit table
mov #ssr0,r2 ; ptr to ssr0
mov #ssr1,r3 ; ptr to ssr3
mov #mmr0,r2 ; ptr to mmr0
mov #mmr1,r3 ; ptr to mmr3
;
reset
mov (r1),(r2) ; no regs changed !
Expand Down Expand Up @@ -574,18 +575,18 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table
mov (r1)+,(r2)+ ; r1,2,r2,2 00010 010 00010 001 via ale
hcmpeq (r3),#^b0001001000010001;
;
; check that index reads are not accounted in ssr1
; check that index reads are not accounted in mmr1
reset
tst (r1)+ ; bump ptr beyond ard
mov -(r1),-2(r2) ; r1,-1 00000 000 11110 001 via ard
hcmpeq (r3),#^b0000000011110001;
;
; check @(pc)+ behavior
; Simh only adds 'general purpose register updates, thus not pc
; w11 updates ssr1 in this case, as is also expected in ekbee1
; w11 updates mmr1 in this case, as is also expected in ekbee1
; case commented out to ensure that cpu_mmu.mac runs on both
;; reset
;; mov -(r1),@#ssr0 ; r1,-2,pc,2 00010 111 11110 001 via ale
;; mov -(r1),@#mmr0 ; r1,-2,pc,2 00010 111 11110 001 via ale
;; hcmpeq (r3),#^b0001011111110001;
;
reset
Expand Down

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