w11: PDP 11/70 CPU and SoC
The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with memory management unit, but without floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RH70/RP06, TM11/TU10) and a rather complete set of UNIBUS peripherals (DL11, LP11, PC11, DZ11, and DEUNA), and last but not least a cache and memory controllers for SRAM, PSRAM and SDRAM (via Xilinx MIG core). The design is FPGA proven, runs currently on Digilent Arty A7, Basys3, Cmod A7, Nexys A7, Nexys4, Nexys3, Nexys2 and S3board boards and boots 5th Edition UNIX and 2.11BSD UNIX.
For more information look into:
- w11 project home page and blog
- change log and installation notes
- guides to build bit files and test benches with Xilinx Vivado and Xilinx ISE
- guides to run test benches and to boot operating systems
- known issues
- known differences
- the impatient readers can try their luck with the quick start guide
A short description of the directory layout is provided separately, the top level directories are
|rtl||HDL sources (mostly vhdl)|
Note on freecores/w11
The full text of the GPL license is in this directory as License.txt.