PDP-11/70 CPU core and SoC
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README.md

w11: PDP 11/70 CPU and SoC

Build Status Coverity Status

Overview

The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with memory management unit, but without floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RK70/RP06, TM11/TU10) and a basic set of UNIBUS peripherals (DL11, LP11, PC11), and last but not least a cache and memory controllers for SRAM and PSRAM. The design is FPGA proven, runs currently on Digilent Arty, Basys3, CmodA7, Nexys4, Nexys3, Nexys2 and S3board boards and boots 5th Edition UNIX and 2.11BSD UNIX.

For more information look into:

A short description of the directory layout is provided separately, the top level directories are

Directory Content
doc documentation
rtl HDL sources (mostly vhdl)
tools many tools

Note on freecores/w11

The freecores team created in 2014 a copy of almost all OpenCores cores in Github under freecores. This created freecores/w11 which is outdated and not maintained. Only wfjm/w11 is maintained.

License

This project is released under the GPL V3 license, all files contain the disclaimer:

This program is free software; you may redistribute and/or modify
it under the terms of the GNU General Public License version 3.
See License.txt in distribition directory for further details.

The full text of the GPL license is in this directory as License.txt.