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Table of Contents Implementation Context Major Subsystems Primary Z80 Signals Memory Map Dual-Port RAM Video Generator Audio Z80 Signals Memory Map Programmable Sound Generators Audio Filters and Mixing

Implementation Context

• 36.864 MHz master clock
• 24-bit RGB+sync video output
• 18-bit 48kHz audio output
• discrete control panel inputs

Major Subsystems

+---------+ +-------+ +-------+ | Primary |==>| DPRAM |==>| Video |==> 24-bit RGB | Z80 | | | | Gen | +---------+ +-------+ +-------+ | ^ | \ +----------+ | ---| Controls | | +----------+ | V +---------+ +-------+ +---------+ | Audio |==>| PSG 1 |==>| Filter, |==> 18-bit samples | Z80 |==>| PSG 2 |==>| Mixer | +---------+ +-------+ +---------+

Primary Z80

Signals

Signal	Direction	Connection
nM1	from Z80	not connected
nRD	from Z80	custom logic for peripheral strobes
nHALT	from Z80	not connected
nNMI	to Z80	driven by vertical blanking signal from video circuit
nBUSACK	from Z80	not connected
nMREQ	from Z80	custom logic for peripheral strobes
nWR	from Z80	custom logic for peripheral strobes
nWAIT	to Z80	custom logic for peripherals
nRESET	to Z80	driven by power-on-reset circuit
nCLK	to Z80	3.072 MHz derived from 18.432 oscillator
nIORQ	from Z80	not connected
nRFSH	from Z80	custom logic for peripheral strobes
nINT	to Z80	permanently de-asserted
nBUSRQ	to Z80	permanently de-asserted
A15:0	from Z80	connected to RAMs, ROMs, and peripherals
D7:0	to/from Z80	connected to RAMs, ROMs, and peripherals

Memory Map

Range	R/W	Size	Target
0x0000-0x5fff	R	24 kiB	ROM (tm1..tm3)
0xa000-0xa3ff	R/W	1 kiB	Tile Color RAM
0xa400-0xa7ff	R/W	1 kiB	Tile Video RAM
0xa800-0xafff	R/W	2 kiB	Program RAM
0xb000-0xb7ff	R/W	2 kiB	Sprite RAM
0xc000	R	1 byte	Video scan line
0xc000	W	1 byte	Sound command register
0xc200	R	1 byte	DIP switch 2
0xc200	W	1 byte	watchdog
0xc300	R	1 byte	Discrete inputs 1
0xc300	W	1 byte	NMI enable gate
0xc302	W	1 byte	Flip screen control
0xc304	W	1 byte	Sound IRQ trigger
0xc30a	W	1 byte	Coin counter
0xc320	R	1 byte	Discrete inputs 2
0xc340	R	1 byte	Discrete inputs 3
0xc360	R	1 byte	DIP switch 1

Dual-Port RAM

Offset	Size	Content
0x0000-0x3fff	16 kiB	Sprite bitmap ROM (tm4, tm5)
0x4000-0x5fff	8 kiB	Tile bitmap ROM (tm6)
0x6800-0x6fff	2 kiB	Sprite RAM
0x7000-0x73ff	1 kiB	Tile color RAM
0x7400-0x77ff	1 kiB	Tile video RAM
0x7800-0x78ff	256 bytes	Sprite palette ROM (timeplt.e9)
0x7900-0x79ff	256 bytes	Time palette ROM (timeplt.e12)

Video Generator

Refer to Video Generator

Audio Z80

Signals

Signal	Direction	Connection
nM1	from Z80	custom logic to clear interrupt source
nRD	from Z80	custom logic for peripheral strobes
nHALT	from Z80	not connected
nNMI	to Z80	permanently de-asserted
nBUSACK	from Z80	not connected
nMREQ	from Z80	custom logic for peripheral strobes
nWR	from Z80	custom logic for peripheral strobes
nWAIT	to Z80	permanently de-asserted
nRESET	to Z80	driven by power-on reset circuit
nCLK	to Z80	1.7985 MHz divided from 14.318 MHz oscillator
nIORQ	from Z80	custom logic to clear interrupt source
nFRSH	from Z80	custom logic for peripheral strobes
nINT	to Z80	dedicate FF set by primary Z80
nBUSRQ	to Z80	permanently de-asserted
A15:0	from Z80	connected to RAM, ROM, and peripherals
D7:0	to/from Z80	connected to RAM, ROM, and peripherals

Memory Map

Range	R/W	Size	Target
0x0000-0x0fff	R	4 kiB	ROM (tm7)
0x3000-0x33ff	R/W	1 kiB	RAM
0x4000	R/W	1 byte	PSG1 data
0x5000	W	1 byte	PSG1 register select
0x6000	R/W	1 byte	PSG2 data
0x7000	W	1 byte	PSG2 register select
0x8000-0xffff	W	32 kiB	filter select (by address bits)

Programmable Sound Generators

Refer to Programmable Sound Generators

Audio Filters and Mixing

Refer to Audio Filters and Mixing