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My second attempt at writing a ST8 device tree. No warnings outputted…
… by DTC this time.
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/* | ||
* arch/arm/boot/dts/panel-a-wuxga-8-0.dtsi | ||
* | ||
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License as published by | ||
* the Free Software Foundation; either version 2 of the License, or | ||
* (at your option) any later version. | ||
* | ||
* This program is distributed in the hope that it will be useful, but WITHOUT | ||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
* more details. | ||
* | ||
* You should have received a copy of the GNU General Public License along | ||
* with this program; if not, write to the Free Software Foundation, Inc., | ||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
*/ | ||
#include <dt-bindings/display/tegra-dc.h> | ||
#include <dt-bindings/display/tegra-panel.h> | ||
|
||
/ { | ||
host1x { | ||
dsi { | ||
panel-a-wuxga-8-0 { | ||
status = "disabled"; | ||
compatible = "a,wuxga-8-0"; | ||
nvidia,dsi-instance = <DSI_INSTANCE_0>; | ||
nvidia,dsi-n-data-lanes = <4>; | ||
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>; | ||
nvidia,dsi-refresh-rate = <60>; | ||
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>; | ||
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>; | ||
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>; | ||
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>; | ||
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>; | ||
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>; | ||
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>; | ||
disp-default-out { | ||
nvidia,out-type = <TEGRA_DC_OUT_DSI>; | ||
nvidia,out-width = <107>; | ||
nvidia,out-height = <172>; | ||
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>; | ||
nvidia,out-parent-clk = "pll_d_out0"; | ||
nvidia,out-xres = <1200>; | ||
nvidia,out-yres = <1920>; | ||
}; | ||
display-timings { | ||
1200x1920-32 { | ||
clock-frequency = <155774400>; | ||
hactive = <1200>; | ||
vactive = <1920>; | ||
hfront-porch = <64>; | ||
hback-porch = <54>; | ||
hsync-len = <10>; | ||
vfront-porch = <3>; | ||
vback-porch = <30>; | ||
vsync-len = <2>; | ||
nvidia,h-ref-to-sync = <4>; | ||
nvidia,v-ref-to-sync = <1>; | ||
}; | ||
}; | ||
smartdimmer { | ||
status = "okay"; | ||
nvidia,turn-off-brightness = <50>; | ||
nvidia,turn-on-brightness = <75>; | ||
nvidia,use-auto-pwm = <0>; | ||
nvidia,hw-update-delay = <0>; | ||
nvidia,bin-width = <0xffffffff>; | ||
nvidia,aggressiveness = <5>; | ||
nvidia,use-vid-luma = <0>; | ||
nvidia,phase-in-settings = <0>; | ||
nvidia,phase-in-adjustments = <0>; | ||
nvidia,k-limit-enable = <1>; | ||
nvidia,k-limit = <200>; | ||
nvidia,sd-window-enable = <0>; | ||
nvidia,soft-clipping-enable= <1>; | ||
nvidia,soft-clipping-threshold = <128>; | ||
nvidia,smooth-k-enable = <1>; | ||
nvidia,smooth-k-incr = <4>; | ||
nvidia,coeff = <5 9 2>; | ||
nvidia,fc = <0 0>; | ||
nvidia,blp = <1024 255>; | ||
nvidia,bltf = <57 65 73 82 | ||
92 103 114 125 | ||
138 150 164 178 | ||
193 208 224 241>; | ||
nvidia,lut = <255 255 255 | ||
199 199 199 | ||
153 153 153 | ||
116 116 116 | ||
85 85 85 | ||
59 59 59 | ||
36 36 36 | ||
17 17 17 | ||
0 0 0>; | ||
nvidia,use-vpulse2 = <1>; | ||
nvidia,bl-device-name = "pwm-backlight"; | ||
}; | ||
cmu { | ||
nvidia,cmu-csc = < 0x0f7 0x3f2 0x016 | ||
0x3f4 0x101 0x3e2 | ||
0x3ff 0x3ff 0x0de >; | ||
nvidia,cmu-lut2 = < 0 1 3 4 6 7 8 9 | ||
11 12 13 14 15 16 17 18 | ||
19 19 20 21 22 22 23 23 | ||
24 25 25 26 26 26 27 27 | ||
28 28 28 29 29 29 30 30 | ||
30 31 31 31 31 32 32 32 | ||
33 33 33 33 34 34 34 35 | ||
35 35 35 36 36 36 37 37 | ||
37 37 38 38 38 38 39 39 | ||
39 40 40 40 40 41 41 41 | ||
42 42 42 42 43 43 43 43 | ||
44 44 44 44 45 45 45 45 | ||
46 46 46 46 47 47 47 47 | ||
48 48 48 48 49 49 49 49 | ||
50 50 50 50 50 51 51 51 | ||
51 52 52 52 52 52 53 53 | ||
53 53 53 54 54 54 54 54 | ||
55 55 55 55 55 55 56 56 | ||
56 56 56 57 57 57 57 57 | ||
57 58 58 58 58 58 58 59 | ||
59 59 59 59 59 60 60 60 | ||
60 60 60 61 61 61 61 61 | ||
61 62 62 62 62 62 62 63 | ||
63 63 63 63 63 63 64 64 | ||
64 64 64 64 65 65 65 65 | ||
65 65 65 66 66 66 66 66 | ||
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68 68 68 68 68 68 68 69 | ||
69 69 69 69 69 70 70 70 | ||
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71 71 71 72 72 72 72 72 | ||
72 72 73 73 73 73 73 73 | ||
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74 75 75 75 75 75 75 75 | ||
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78 78 78 78 78 78 78 79 | ||
79 79 79 79 79 79 79 80 | ||
80 80 80 80 80 80 80 81 | ||
81 81 81 81 81 81 81 81 | ||
82 82 82 82 82 82 82 82 | ||
82 83 83 83 83 83 83 83 | ||
83 83 84 84 84 84 84 84 | ||
84 84 84 85 85 85 85 85 | ||
85 85 85 85 86 86 86 86 | ||
86 86 86 86 86 86 87 87 | ||
87 87 87 87 87 87 87 87 | ||
88 88 88 88 88 88 88 88 | ||
88 88 88 89 89 89 89 89 | ||
89 89 89 89 89 90 90 90 | ||
90 90 90 90 90 90 90 90 | ||
91 91 91 91 91 91 91 91 | ||
91 91 91 92 92 92 92 92 | ||
92 92 92 92 92 92 93 93 | ||
93 93 93 93 93 93 93 93 | ||
93 93 94 94 94 94 94 94 | ||
94 94 94 94 94 95 95 95 | ||
95 95 95 95 95 95 95 95 | ||
96 96 96 96 96 96 96 96 | ||
96 96 96 97 97 97 97 97 | ||
97 97 97 97 97 97 97 98 | ||
98 98 98 98 98 98 98 98 | ||
98 98 99 99 99 99 99 99 | ||
99 99 99 99 99 100 100 100 | ||
100 101 102 103 103 104 105 105 | ||
106 107 108 108 109 110 110 111 | ||
112 112 113 114 114 115 115 116 | ||
117 117 118 119 119 120 120 121 | ||
121 122 123 123 124 124 125 125 | ||
126 126 127 127 128 128 129 129 | ||
130 130 131 131 132 132 133 133 | ||
134 134 135 135 136 136 137 137 | ||
137 138 138 139 139 140 140 141 | ||
141 142 142 142 143 143 144 144 | ||
145 145 146 146 147 147 148 148 | ||
149 149 149 150 150 151 151 152 | ||
152 153 153 154 154 154 155 155 | ||
156 156 157 157 158 158 158 159 | ||
159 160 160 160 161 161 162 162 | ||
162 163 163 163 164 164 165 165 | ||
165 166 166 166 167 167 167 168 | ||
168 168 169 169 169 170 170 170 | ||
171 171 171 172 172 172 173 173 | ||
173 174 174 174 175 175 175 176 | ||
176 177 177 177 178 178 178 179 | ||
179 179 180 180 181 181 181 182 | ||
182 183 183 183 184 184 184 185 | ||
185 186 186 186 187 187 188 188 | ||
188 189 189 189 190 190 191 191 | ||
191 192 192 192 193 193 193 194 | ||
194 194 195 195 196 196 196 197 | ||
197 197 198 198 198 198 199 199 | ||
199 200 200 200 201 201 201 202 | ||
202 202 203 203 203 203 204 204 | ||
204 205 205 205 205 206 206 206 | ||
207 207 207 207 208 208 208 209 | ||
209 209 209 210 210 210 211 211 | ||
211 211 212 212 212 212 213 213 | ||
213 214 214 214 214 215 215 215 | ||
215 216 216 216 217 217 217 217 | ||
218 218 218 218 219 219 219 219 | ||
220 220 220 220 221 221 221 222 | ||
222 222 222 223 223 223 223 224 | ||
224 224 224 225 225 225 225 226 | ||
226 226 226 227 227 227 227 228 | ||
228 228 228 229 229 229 230 230 | ||
230 230 231 231 231 231 232 232 | ||
232 232 233 233 233 233 234 234 | ||
234 234 235 235 235 235 236 236 | ||
236 236 237 237 237 237 238 238 | ||
238 238 238 239 239 239 239 240 | ||
240 240 240 241 241 241 241 242 | ||
242 242 242 243 243 243 243 243 | ||
244 244 244 244 245 245 245 245 | ||
246 246 246 246 246 247 247 247 | ||
247 248 248 248 248 248 249 249 | ||
249 249 249 250 250 250 250 251 | ||
251 251 251 251 252 252 252 252 | ||
252 253 253 253 253 253 254 254 | ||
254 254 254 255 255 255 255 255 >; | ||
}; | ||
}; | ||
}; | ||
}; | ||
backlight { | ||
compatible = "pwm-backlight"; | ||
status = "okay"; | ||
panel-a-wuxga-8-0-bl { | ||
status = "disabled"; | ||
compatible = "a,wuxga-8-0-bl"; | ||
pwms = <&pwm 1 40161>; | ||
max-brightness = <255>; | ||
default-brightness = <191>; | ||
default-charge-brightness = <112>; | ||
bl-measured = < 0 1 2 4 5 6 7 8 | ||
10 11 12 13 14 14 15 16 | ||
17 18 18 19 20 21 22 23 | ||
24 25 26 27 28 29 30 31 | ||
32 33 34 35 36 37 38 39 | ||
40 41 42 43 44 45 46 47 | ||
48 49 50 51 52 53 54 55 | ||
55 56 57 58 59 60 61 62 | ||
63 64 65 66 67 68 69 70 | ||
71 72 73 74 75 76 77 78 | ||
79 80 81 82 83 84 85 86 | ||
87 88 89 90 91 92 93 94 | ||
95 96 97 98 99 100 101 102 | ||
103 104 105 106 107 108 109 110 | ||
111 112 113 114 115 116 117 118 | ||
119 120 121 122 123 124 125 126 | ||
127 128 129 130 131 132 133 134 | ||
135 136 137 138 139 140 141 142 | ||
143 144 145 146 147 148 149 150 | ||
151 152 153 154 155 156 157 158 | ||
159 160 161 162 163 164 165 166 | ||
167 168 169 170 171 172 173 174 | ||
175 176 177 178 179 180 181 182 | ||
183 184 185 186 187 188 189 190 | ||
191 192 193 194 195 196 197 198 | ||
199 200 201 202 203 204 205 206 | ||
207 208 209 210 211 212 213 214 | ||
215 216 217 218 219 220 221 222 | ||
223 224 225 226 227 228 229 230 | ||
231 232 233 234 235 236 237 238 | ||
239 240 241 242 243 244 245 246 | ||
247 248 249 250 251 253 254 255 >; | ||
bl-nonlinear = < 0 1 1 2 2 3 3 4 | ||
4 5 5 6 7 7 8 8 | ||
9 9 10 10 11 11 12 12 | ||
13 14 14 15 15 16 16 17 | ||
17 18 18 19 20 20 21 21 | ||
22 22 23 23 24 24 25 25 | ||
26 27 27 28 28 29 29 30 | ||
30 31 31 32 33 33 34 34 | ||
35 35 36 36 37 37 38 38 | ||
39 40 40 41 41 42 42 43 | ||
43 44 44 45 46 46 47 47 | ||
48 48 49 49 50 50 51 52 | ||
52 53 53 54 54 55 55 56 | ||
56 57 57 58 59 59 60 60 | ||
61 61 62 62 63 63 64 65 | ||
65 66 66 67 67 68 68 69 | ||
69 70 70 71 72 72 73 73 | ||
74 74 75 75 76 76 77 78 | ||
78 79 79 80 80 81 81 82 | ||
82 83 83 84 85 85 86 86 | ||
87 87 88 88 89 89 90 92 | ||
94 96 97 99 101 103 105 107 | ||
109 110 112 114 116 118 120 122 | ||
123 125 127 129 131 133 134 136 | ||
138 140 142 144 146 147 149 151 | ||
153 155 157 159 160 162 164 166 | ||
168 170 172 173 175 177 179 181 | ||
183 185 186 188 190 192 194 196 | ||
198 199 201 203 205 207 209 211 | ||
212 214 216 218 220 222 223 225 | ||
227 229 231 233 235 236 238 240 | ||
242 244 246 248 249 251 253 255 >; | ||
}; | ||
}; | ||
}; |
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arch/arm/boot/dts/tegra124-platforms/tegra124-st8-clocks-timers-rtc.dtsi
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/ { | ||
clocks { | ||
compatible = "simple-bus"; | ||
#address-cells = <0x1>; | ||
#size-cells = <0x0>; | ||
status = "okay"; | ||
|
||
clk32k_in: clock { | ||
compatible = "fixed-clock"; | ||
reg = <0x0>; | ||
#clock-cells = <0x0>; | ||
clock-frequency = <32768>; | ||
linux,phandle = <0x11>; | ||
phandle = <0x11>; | ||
}; | ||
}; | ||
|
||
tegra_car: clock@0,60006000 { | ||
compatible = "nvidia,tegra124-car"; | ||
clocks = <&clk32k_in>; | ||
status = "okay"; | ||
}; | ||
|
||
timer@60005000 { | ||
compatible = "nvidia,tegra-nvtimer"; | ||
reg = <0x0 0x60005000 0x0 0x400>; | ||
interrupts = <0x0 0x0 0x4 | ||
0x0 0x1 0x4 | ||
0x0 0x29 0x4 | ||
0x0 0x2a 0x4 | ||
0x0 0x79 0x4 | ||
0x0 0x97 0x4 | ||
0x0 0x98 0x4 | ||
0x0 0x99 0x4 | ||
0x0 0x9a 0x4 | ||
0x0 0x9b 0x4 | ||
0x0 0x7a 0x4>; | ||
clocks = <&tegra_car 0x5>; | ||
status = "okay"; | ||
}; | ||
|
||
timer { | ||
compatible = "arm,armv7-timer"; | ||
interrupts = <0x1 0xd 0xf04 | ||
0x1 0xe 0xf04>; | ||
}; | ||
|
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dfll@70110000 { | ||
compatible = "nvidia,tegra124-dfll"; | ||
reg = <0x0 0x70110000 0x0 0x400>; | ||
out-clock-name = "dfll_cpu"; | ||
status = "okay"; | ||
board-params = <0x15>; | ||
i2c-pmic-integration = <0x16>; | ||
}; | ||
|
||
rtc1: rtc { | ||
compatible = "nvidia,tegra-rtc"; | ||
reg = <0x0 0x7000e000 0x0 0x100>; | ||
interrupts = <0x0 0x2 0x4>; | ||
clocks = <&tegra_car 0x4>; | ||
status = "okay"; | ||
}; | ||
|
||
wdt0: watchdog@60005100 { | ||
compatible = "nvidia,tegra-wdt"; | ||
reg = <0x0 0x60005100 0x0 0x20 0x0 0x60005070 0x0 0x8>; | ||
interrupts = <0 123 0x04>; | ||
nvidia,expiry-count = <4>; | ||
nvidia,enable-on-init; | ||
nvidia,heartbeat-init = <120>; | ||
}; | ||
}; |
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