Replace original wording of [Branin1967] by wording of modelica#3830

wischhusen · Jun 6, 2021 · c5ef27b · c5ef27b
1 parent 9301a7a
commit c5ef27b
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/Modelica/Electrical/Analog/Lines/TLine1.mo b/Modelica/Electrical/Analog/Lines/TLine1.mo
@@ -6,8 +6,8 @@ model TLine1
   parameter SI.Resistance Z0(start=1)
     "Characteristic impedance";
   parameter SI.Time TD(start=1) "Transmission delay";
-  SI.Voltage er(start=0) "Reflected voltage wave";
-  SI.Voltage es(start=0) "Incident voltage wave";
+  SI.Voltage es(start=0) "Voltage source of forward travelling wave";
+  SI.Voltage er(start=0) "Voltage source of reflected wave";
 equation
   assert(Z0 > 0, "Z0 has to be positive");
   assert(TD > 0, "TD has to be positive");

diff --git a/Modelica/Electrical/Analog/Lines/TLine2.mo b/Modelica/Electrical/Analog/Lines/TLine2.mo
@@ -7,8 +7,8 @@ model TLine2
     "Characteristic impedance";
   parameter SI.Frequency F(start=1) "Frequency";
   parameter Real NL(start=1) "Normalized length";
-  SI.Voltage er(start=0) "Reflected voltage wave";
-  SI.Voltage es(start=0) "Incident voltage wave";
+  SI.Voltage es(start=0) "Voltage source of forward travelling wave";
+  SI.Voltage er(start=0) "Voltage source of reflected wave";
 protected
   parameter SI.Time TD=NL/F;
 equation

diff --git a/Modelica/Electrical/Analog/Lines/TLine3.mo b/Modelica/Electrical/Analog/Lines/TLine3.mo
@@ -4,8 +4,8 @@ model TLine3
   extends Modelica.Electrical.Analog.Interfaces.TwoPort;
   parameter SI.Resistance Z0(start=1) "Natural impedance";
   parameter SI.Frequency F(start=1) "Frequency";
-  SI.Voltage er(start=0) "Reflected voltage wave";
-  SI.Voltage es(start=0) "Incident voltage wave";
+  SI.Voltage es(start=0) "Voltage source of forward travelling wave";
+  SI.Voltage er(start=0) "Voltage source of reflected wave";
 protected
   parameter SI.Time TD=1/F/4;
 equation