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arm.yaml
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arm.yaml
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architecture_information:
name: arm
## Flag semantic #######################################################
function:
negate_flag: &negate_flag |
nf.id = bit_cast(res.val >> (int(op0.bit, op0.bit) - int(op0.bit, 1)), int16(1));
zero_flag: &zero_flag |
if __expr and res.val == int(op0.bit, 0):
zf.id = int1(1)
else:
zf.id = int1(0);
carry_flag_add: &carry_flag_add |
cf.id = bit_cast(((op0.val ^ op1.val ^ res.val) ^ ((op0.val ^ res.val) & ((op0.val ^ op1.val) ^ int(op0.bit, -1)))) >> (int(op0.bit, op0.bit) - int(op0.bit, 1)), int16(1));
overflow_flag_add: &overflow_flag_add |
vf.id = bit_cast(((op0.val ^ res.val) & ((op0.val ^ op1.val) ^ int(op0.bit, -1))) >> (int(op0.bit, op0.bit) - int(op0.bit, 1)), int16(1));
## Standard flags operations
semantic:
## Arithmetic / logical operations
add2: &add2 |
op0.val = op0.val + op1.val;
add3: &add3 |
op0.val = op1.val + op2.val;
## Data transfer operations
adr: &adr |
op0.val = op1.val;
ldrb: &ldrb |
op0.val = (op0.val & int32(0xffffff00)) | bit_cast(op1.val, int16(8));
ldrh: &ldrh |
op0.val = (op0.val & int32(0xffff0000)) | bit_cast(op1.val, int16(16));
ldr: &ldr |
op0.val = op1.val;
strb: &strb |
op1.val = (op1.val & int32(0xffffff00)) | bit_cast(op0.val, int16(8));
strh: &strh |
op1.val = (op1.val & int32(0xffff0000)) | bit_cast(op0.val, int16(16));
str: &str |
op1.val = op0.val
mov: &mov |
op0.val = op1.val;
movt: &movt |
op0.val = (op0.val & int32(0x0000ffff)) | (op1.val << int32(16));
movw: &movw |
op0.val = (op0.val & int32(0xffff0000)) | (op1.val & int32(0x0000ffff));
## Control flow operations
b: &b |
program.id = op0.val;
# the manual seems unclear about the new value of lr...
bl: &bl |
lr.id = (program.id - insn.size);
program.id = op0.val;
push: &push |
stack.id -= op0.size;
stack.mem = op0.val;
pop: &pop |
op0.val = stack.mem;
stack.id += op0.size;
## Flags manipulation
cmn: &cmn |
alloc_var('res', op0.bit);
res = op0.val + op1.val;
call('negate_flag');
call('zero_flag');
call('carry_flag_add');
call('overflow_flag_add');
free_var('res');
encoding:
- cond: &cond [ 'c','c','c','c' ]
- imm_1: &imm_1 [ 'i' ]
- imm_2: &imm_2 [ 'i','i' ]
- imm_3: &imm_3 [ 'i','i','i' ]
- imm_4: &imm_4 [ 'i','i','i','i' ]
- imm_4L: &imm_4L [ 'i','i','i','i' ]
- imm_4H: &imm_4H [ 'i','i','i','i' ]
- imm_5: &imm_5 [ 'i','i','i','i','i' ]
- imm_6: &imm_6 [ 'i','i','i','i','i','i' ]
- imm_7: &imm_7 [ 'i','i','i','i','i','i','i' ]
- imm_8: &imm_8 [ 'i','i','i','i','i','i','i','i' ]
- imm_10: &imm_10 [ 'i','i','i','i','i','i','i','i','i','i' ]
- imm_10L: &imm_10L [ 'i','i','i','i','i','i','i','i','i','i' ]
- imm_10H: &imm_10H [ 'i','i','i','i','i','i','i','i','i','i' ]
- imm_11: &imm_11 [ 'i','i','i','i','i','i','i','i','i','i','i' ]
- imm_12: &imm_12 [ 'i','i','i','i','i','i','i','i','i','i','i','i' ]
- imm_24: &imm_24 [ 'i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i','i' ]
- Ra_4: &Ra_4 [ 'a','a','a','a' ]
- Rd_3: &Rd_3 [ 'd','d','d' ]
- Rd_4: &Rd_4 [ 'd','d','d','d' ]
- Rm_3: &Rm_3 [ 'm','m','m' ]
- Rm_4: &Rm_4 [ 'm','m','m','m' ]
- RmDup_4: &RmDup_4 [ 'md', 'md', 'md', 'md' ]
- Rn_3: &Rn_3 [ 'n','n','n' ]
- Rn_4: &Rn_4 [ 'n','n','n','n' ]
- Rs_4: &Rs_4 [ 's','s','s','s' ]
- Rt_3: &Rt_3 [ 't','t','t' ]
- Rt_4: &Rt_4 [ 't','t','t','t' ]
- Va: &Va [ 'a','a','a','a' ]
- Vd: &Vd [ 'd','d','d','d' ]
- Vm: &Vm [ 'm','m','m','m' ]
- Vn: &Vn [ 'n','n','n','n' ]
- Vs: &Vs [ 's','s','s','s' ]
- Vt: &Vt [ 't','t','t','t' ]
- Rt2_4: &Rt2_4 [ 't2','t2','t2','t2' ]
- RdLo_4: &RdLo_4 [ 'dlo','dlo','dlo','dlo' ]
- RdHi_4: &RdHi_4 [ 'dhi','dhi','dhi','dhi' ]
- Rdm_3: &Rdm_3 [ 'dm','dm','dm' ]
- Rdm_4: &Rdm_4 [ 'dm','dm','dm','dm' ]
- Rdn_3: &Rdn_3 [ 'dn','dn','dn' ]
- Rdn_4: &Rdn_4 [ 'dn','dn','dn','dn' ]
- CRd_4: &CRd_4 [ 'd','d','d','d' ]
- CRm_4: &CRm_4 [ 'm','m','m','m' ]
- CRn_4: &CRn_4 [ 'n','n','n','n' ]
- a: &a [ 'A' ]
- b_size: &b_size [ 'B' ]
- e_size: &e_size [ 'E' ]
- B: &B [ 'B' ]
- D: &D [ 'D' ]
- E: &E [ 'E' ]
- F: &F [ 'F' ]
- H: &H [ 'H' ]
- J: &J [ 'J' ]
- L: &L [ 'L' ]
- M: &M [ 'M' ]
- N: &N [ 'N' ]
- P: &P [ 'P' ]
- Q: &Q [ 'Q' ]
- R: &R [ 'R' ]
- S: &S [ 'S' ]
- T: &T [ 'T' ]
- U: &U [ 'U' ]
- W: &W [ 'W' ]
- DN: &DN [ 'DN' ]
- DM: &DM [ 'DM' ]
- J1: &J1 [ 'J1' ]
- J2: &J2 [ 'J2' ]
- type_2: &type_2 [ 'tp','tp' ]
- type_4: &type_4 [ 'tp','tp','tp','tp' ]
- lsb: &lsb [ 'lsb','lsb','lsb','lsb','lsb' ]
- msb: &msb [ 'msb','msb','msb','msb','msb' ]
- op_1: &op_1 [ 'op' ]
- op_2: &op_2 [ 'op','op' ]
- op2_2: &op2_2 [ 'op','op' ]
- coproc: &coproc [ 'coproc','coproc','coproc','coproc' ]
- opc1_2: &opc1_2 [ 'opc1','opc1' ]
- opc1_3: &opc1_3 [ 'opc1','opc1','opc1' ]
- opc1_4: &opc1_4 [ 'opc1','opc1','opc1','opc1' ]
- opc2_2: &opc2_2 [ 'opc2','opc2' ]
- opc2_3: &opc2_3 [ 'opc2','opc2','opc2' ]
- option: &option [ 'option','option','option','option' ]
- firstcond: &firstcond [ 'firstcond','firstcond','firstcond','firstcond' ]
- mask_2: &mask_2 [ 'mask_4','mask_4' ]
- mask_4: &mask_4 [ 'mask_4','mask_4','mask_4','mask_4' ]
- register_list_8: ®ister_list_8 [ 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r' ]
- register_list_13: ®ister_list_13 [ 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r' ]
- register_list_16: ®ister_list_16 [ 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r', 'r' ]
- tb: &tb [ 'tb' ]
- widthm1: &widthm1 [ 'widthm1','widthm1','widthm1','widthm1','widthm1' ]
- SBZ: &SBZ [ 'sbz','sbz','sbz','sbz' ]
- sh: &sh [ 'sh' ]
- sat_imm_4: &sat_imm_4 [ 'i','i','i','i' ]
- sat_imm_5: &sat_imm_5 [ 'sat_imm_5','sat_imm_5','sat_imm_5','sat_imm_5','sat_imm_5' ]
- rotate: &rotate [ 'rotate','rotate' ]
- size: &size [ 'i','i' ]
- sz: &sz [ 'sz' ]
- cmode: &cmode [ 'cmode','cmode','cmode','cmode' ]
- sf: &sf [ 'sf' ]
- sx: &sx [ 'sx' ]
- align: &align [ 'align','align' ]
- index_align: &index_align [ 'index_align','index_align','index_align','index_align' ]
- len: &len [ 'len','len' ]
- handler5: &handler5 [ 'h','h','h','h','h' ]
- handler8: &handler8 [ 'h','h','h','h','h','h','h','h' ]
instruction:
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADC{S}<c> <Rd>, <Rn>, #<imm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,0,1,0,1,0,*S,*Rn_4,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADC{S}<c> <Rd>, <Rn>, #<arm_expand_imm>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,1,0,1,*S,*Rn_4,*Rd_4,*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADCS <Rdn>, <Rm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,0,0,1,0,1,*Rm_3,*Rdn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADC{S}<c>.W <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,1,0,1,0,*S,*Rn_4,(0),*imm_3,*Rd_4,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADC{S}<c> <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,1,0,1,*S,*Rn_4,*Rd_4,*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADC{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,1,0,1,*S,*Rn_4,*Rd_4,*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADDS <Rd>, <Rn>, #<imm>'
semantic: *add3
mode: T1
attribute: []
encoding: [ 0,0,0,1,1,1,0,*imm_3,*Rn_3,*Rd_3 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADDS <Rdn>, #<imm>'
semantic: *add3
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 0,0,1,1,0,*Rdn_3,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADD{S}<c>.W <Rd>, <Rn>, #<imm>'
semantic: *add3
mode: T3
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,0,1,0,0,0,*S,*Rn_4,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADDW<c> <Rd>, <Rn>, #<imm>'
semantic: []
mode: T4
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,1,0,0,0,0,0,*Rn_4,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD{S}<c> <Rd>, <Rn>, #<arm_expand_imm>'
semantic: *add3
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,1,0,0,*S,*Rn_4,*Rd_4,*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADDS <Rd>, <Rn>, <Rm>'
semantic: *add3
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,0,0,1,1,0,0,*Rm_3,*Rn_3,*Rd_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADD<c> <Rdn>, <Rm>'
semantic: *add2
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,1,0,0,*DN,*Rm_4,*Rdn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADD{S}<c>.W <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: T3
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,1,0,0,0,*S,*Rn_4,(0),*imm_3,*Rd_4,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD{S}<c> <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: *add3
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,1,0,0,*S,*Rn_4,*Rd_4,*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,1,0,0,*S,*Rn_4,*Rd_4,*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD<c> <Rd>, SP, #<imm>'
semantic: *add3
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,0,1,0,1,*Rd_3,*imm_8 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD<c> SP, SP, #<imm>'
semantic: *add3
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,0,1,1,0,0,0,0,0,*imm_7 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADD{S}<c>.W <Rd>, SP, #<imm>'
semantic: []
mode: T3
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,0,1,0,0,0,*S,1,1,0,1,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADDW<c> <Rd>, SP, #<imm>'
semantic: []
mode: T4
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,1,0,0,0,0,0,1,1,0,1,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD{S}<c> <Rd>, SP, #<arm_expand_imm>'
semantic: *add3
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,1,0,0,*S,1,1,0,1,*Rd_4,*imm_12 ]
# FIXME: remove the last operand (<Rdm>)
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD<c> <Rdm>, SP'
semantic: *add2
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,1,0,0,*DM,1,1,0,1,*Rdm_3 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD<c> SP,<Rm>'
semantic: *add2
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,1,0,0,1,*Rm_4,1,0,1 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADD{S}<c>.W <Rd>, SP, <Rm>{,<shift>}'
semantic: *add3
mode: T3
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,1,0,0,0,*S,1,1,0,1,0,*imm_3,*Rd_4,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADD{S}<c> <Rd>, SP, <Rm>{,<shift>}'
semantic: *add3
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,1,0,0,*S,1,1,0,1,*Rd_4,*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADR<c> <Rd>, <label>'
semantic: *adr
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,0,1,0,0,*Rd_3,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'SUB <Rd>, PC, #0'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,1,0,1,0,1,0,1,1,1,1,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ADR<c>.W <Rd>, <label>'
semantic: *adr
mode: T3
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,1,0,0,0,0,0,1,1,1,1,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ADR<c> <Rd>, <arm_expand_label>'
semantic: *adr
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,1,0,0,0,1,1,1,1,*Rd_4,*imm_12 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'SUB <Rd>, PC, #0'
semantic: []
mode: A2
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,0,1,0,0,1,1,1,1,*Rd_4,*imm_12 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'AND{S}<c> <Rd>, <Rn>, #<imm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,0,0,0,0,0,*S,*Rn_4,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'AND{S}<c> <Rd>, <Rn>, #<arm_expand_imm_c>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,0,0,0,*S,*Rn_4,*Rd_4,*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ANDS <Rdn>, <Rm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,0,0,0,0,0,*Rm_3,*Rdn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'AND{S}<c>.W <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,0,0,0,0,*S,*Rn_4,(0),*imm_3,*Rd_4,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'AND{S}<c> <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,0,0,0,*S,*Rn_4,*Rd_4,*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'AND{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,0,0,0,*S,*Rn_4,*Rd_4,*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ASRS <Rd>, <Rm>, #<imm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,0,0,1,0,*imm_5,*Rm_3,*Rd_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ASR{S}<c>.W <Rd>, <Rm>, #<imm>'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,0,0,1,0,*S,1,1,1,1,(0),*imm_3,*Rd_4,*imm_2,1,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ASR{S}<c> <Rd>, <Rm>, #<imm>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,1,1,0,1,*S,(0),(0),(0),(0),*Rd_4,*imm_5,1,0,0,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ASRS <Rdn>, <Rm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,0,0,1,0,0,*Rm_3,*Rdn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'ASR{S}<c>.W <Rd>, <Rn>, <Rm>'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,1,0,1,0,0,1,0,*S,*Rn_4,1,1,1,1,*Rd_4,0,0,0,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'ASR{S}<c> <Rd>, <Rn>, <Rm>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,1,1,0,1,*S,(0),(0),(0),(0),*Rd_4,*Rm_4,0,1,0,1,*Rn_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'B<c> <thumb_branch_label>'
semantic: *b
mode: T1
attribute: [ 'jmp' ]
encoding: [ 1,1,0,1,*cond,*imm_8 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'B<c> <thumb_branch_label>'
semantic: *b
mode: T2
attribute: [ 'jmp' ]
encoding: [ 1,1,1,0,0,*imm_11 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'B<c>.W <thumb_branch_label>'
semantic: *b
mode: T3
attribute: [ 'jmp' ]
encoding: [ 1,1,1,1,0,*S,*cond,*imm_6,1,0,*J1,0,*J2,*imm_11 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'B<c>.W <thumb_branch_label>'
semantic: *b
mode: T4
attribute: ['jmp']
encoding: [ 1,1,1,1,0,*S,*imm_10,1,0,*J1,1,*J2,*imm_11 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'B<c> <arm_branch_label>'
semantic: *b
mode: A1
attribute: [ 'jmp' ]
encoding: [ *cond,1,0,1,0,*imm_24 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BFC<c> <Rd>, #<lsb>, #<width>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,(0),1,1,0,1,1,0,1,1,1,1,0,*imm_3,*Rd_4,*imm_2,(0),*msb ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BFC<c> <Rd>, #<lsb>, #<width>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,1,1,1,1,1,0,*msb,*Rd_4,*lsb,0,0,1,1,1,1,1 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BFI<c> <Rd>, <Rn>, #<lsb>, #<width>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,(0),1,1,0,1,1,0,*Rn_4,0,*imm_3,*Rd_4,*imm_2,(0),*msb ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BFI<c> <Rd>, <Rn>, #<lsb>, #<width>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,1,1,1,1,1,0,*msb,*Rd_4,*lsb,0,0,1,*Rn_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BIC{S}<c> <Rd>, <Rn>, #<imm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,0,0,0,0,1,*S,*Rn_4,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BIC{S}<c> <Rd>, <Rn>, #<arm_expand_imm_c>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,1,1,1,0,*S,*Rn_4,*Rd_4,*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BICS <Rdn>, <Rm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,0,1,1,1,0,*Rm_3,*Rdn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BIC{S}<c>.W <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,0,0,0,1,*S,*Rn_4,(0),*imm_3,*Rd_4,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BIC{S}<c> <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,1,1,1,0,*S,*Rn_4,*Rd_4,*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BIC{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,1,1,1,0,*S,*Rn_4,*Rd_4,*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BKPT #<imm>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,0,1,1,1,1,1,0,*imm_8 ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BKPT #<imm>'
semantic: []
mode: A1
attribute: []
encoding: [ *cond,0,0,0,1,0,0,1,0,*imm_12,0,1,1,1,*imm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BL<c> <thumb_branch_label>'
semantic: *bl
mode: T1
attribute: [ 'call' ]
encoding: [ 1,1,1,1,0,*S,*imm_10,1,1,*J1,1,*J2,*imm_11 ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BLX<c> <label>'
semantic: []
mode: T2
attribute: [ 'thumb_branch_label' ]
encoding: [ 1,1,1,1,0,*S,*imm_10H,1,1,*J1,0,*J2,*imm_10L,0 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BL<c> <arm_branch_label>'
semantic: *bl
mode: A1
attribute: [ 'call' ]
encoding: [ *cond,1,0,1,1,*imm_24 ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BLX <arm_branch_label>'
semantic: []
mode: A2
attribute: [ 'call' ]
encoding: [ 1,1,1,1,1,0,1,*H,*imm_24 ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BLX<c> <Rm>'
semantic: []
mode: T1
attribute: [ 'call' ]
encoding: [ 0,1,0,0,0,1,1,1,1,*Rm_4,(0),(0),(0) ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BLX<c> <Rm>'
semantic: []
mode: A1
attribute: [ 'call' ]
encoding: [ *cond,0,0,0,1,0,0,1,0,(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),0,0,1,1,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BX<c> <Rm>'
semantic: []
mode: T1
attribute: [ 'call' ]
encoding: [ 0,1,0,0,0,1,1,1,0,*Rm_4,(0),(0),(0) ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'BX<c> Rm'
semantic: []
mode: A1
attribute: [ 'call' ]
encoding: [ *cond,0,0,0,1,0,0,1,0,(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),0,0,0,1,*Rm_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'BXJ<c> <Rm>'
semantic: []
mode: T1
attribute: [ 'call', 'change_to_jazelle' ]
encoding: [ 1,1,1,1,0,0,1,1,1,1,0,0,*Rm_4,1,0,(0),0,(1),(1),(1),(1),(0),(0),(0),(0),(0),(0),(0),(0) ]
- processor: ['ARMv5TEJ', 'ARMv6*', 'ARMv7']
format: 'BXJ<c> <Rm>'
semantic: []
mode: A1
attribute: [ 'call' ]
encoding: [ *cond,0,0,0,1,0,0,1,0,(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),(1),0,0,1,0,*Rm_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CB{N}Z <Rn>, <label>'
semantic: []
mode: T1
attribute: [ 'cond', 'jmp' ]
encoding: [ 1,0,1,1,*op_1,0,*imm_1,1,*imm_5,*Rn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>'
semantic: []
mode: T1
attribute: ['support_it_block']
encoding: [ 1,1,1,0,1,1,1,0,*opc1_4,*CRn_4,*CRd_4,*coproc,*opc2_3,0,*CRm_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>'
semantic: []
mode: A1
attribute: []
encoding: [ *cond,1,1,1,0,*opc1_4,*CRn_4,*CRd_4,*coproc,*opc2_3,0,*CRm_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>'
semantic: []
mode: T2
attribute: ['support_it_block']
encoding: [ 1,1,1,1,1,1,1,0,*opc1_4,*CRn_4,*CRd_4,*coproc,*opc2_3,0,*CRm_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>'
semantic: []
mode: A2
attribute: ['support_it_block']
encoding: [ 1,1,1,1,1,1,1,0,*opc1_4,*CRn_4,*CRd_4,*coproc,*opc2_3,0,*CRm_4 ]
- processor: ['ARMv7']
format: 'CLREX<c>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,1,1,1,0,0,1,1,1,0,1,1,(1),(1),(1),(1),1,0,(0),0,(1),(1),(1),(1),0,0,1,0,(1),(1),(1),(1) ]
- processor: ['ARMv6K', 'ARMv7']
format: 'CLREX'
semantic: []
mode: A1
attribute: []
encoding: [ 1,1,1,1,0,1,0,1,0,1,1,1,(1),(1),(1),(1),(1),(1),(1),(1),(0),(0),(0),(0),0,0,0,1,(1),(1),(1),(1) ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CLZ<c> <Rd>, <Rm>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,1,1,1,1,0,1,0,1,0,1,1,*RmDup_4,1,1,1,1,*Rd_4,1,0,0,0,*Rm_4 ]
- processor: ['ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CLZ<c> <Rd>, <Rm>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,1,0,1,1,0,(1),(1),(1),(1),*Rd_4,(1),(1),(1),(1),0,0,0,1,*Rm_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CMN<c> <Rn>, #<thumb_expand_imm>'
semantic: *cmn
mode: T1
attribute: [ 'cond' ]
encoding: [ 1,1,1,1,0,*imm_1,0,1,0,0,0,1,*Rn_4,0,*imm_3,1,1,1,1,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMN<c> <Rn>, #<arm_expand_imm>'
semantic: *cmn
mode: A1
attribute: [ 'cond' ]
encoding: [ *cond,0,0,1,1,0,1,1,1,*Rn_4,(0),(0),(0),(0),*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMN<c> <Rn>, <Rm>'
semantic: *cmn
mode: T1
attribute: [ 'cond' ]
encoding: [ 0,1,0,0,0,0,1,0,1,1,*Rm_3,*Rn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CMN<c>.W <Rn>, <Rm>{,<shift>}'
semantic: []
mode: T2
attribute: [ 'cond' ]
encoding: [ 1,1,1,0,1,0,1,1,0,0,0,1,*Rn_4,(0),*imm_3,1,1,1,1,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMN<c> <Rn>, <Rm>{,<shift>}'
semantic: *cmn
mode: A1
attribute: [ 'cond' ]
encoding: [ *cond,0,0,0,1,0,1,1,1,*Rn_4,(0),(0),(0),(0),*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMN<c> <Rn>, <Rm>, <type> <Rs>'
semantic: *cmn
mode: A1
attribute: [ 'cond' ]
encoding: [ *cond,0,0,0,1,0,1,1,1,*Rn_4,(0),(0),(0),(0),*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMP<c> <Rn>, #<imm>'
semantic: []
mode: T1
attribute: [ 'cond' ]
encoding: [ 0,0,1,0,1,*Rn_3,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CMP<c>.W <Rn>, #<imm>'
semantic: []
mode: T2
attribute: [ 'cond' ]
encoding: [ 1,1,1,1,0,*imm_1,0,1,1,0,1,1,*Rn_4,0,*imm_3,1,1,1,1,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMP<c> <Rn>, #<arm_expand_imm>'
semantic: []
mode: A1
attribute: [ 'cond' ]
encoding: [ *cond,0,0,1,1,0,1,0,1,*Rn_4,(0),(0),(0),(0),*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMP<c> <Rn>, <Rm>'
semantic: []
mode: T1
attribute: [ 'cond' ]
encoding: [ 0,1,0,0,0,0,1,0,1,0,*Rm_3,*Rn_3 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMP<c> <Rn>, <Rm>'
semantic: []
mode: T2
attribute: [ 'cond' ]
encoding: [ 0,1,0,0,0,1,0,1,*N,*Rm_4,*Rn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'CMP<c>.W <Rn>, <Rm> {,<shift>}'
semantic: []
mode: T3
attribute: [ 'cond' ]
encoding: [ 1,1,1,0,1,0,1,1,1,0,1,1,*Rn_4,(0),*imm_3,1,1,1,1,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMP<c> <Rn>, <Rm>{,<shift>}'
semantic: []
mode: A1
attribute: [ 'cond' ]
encoding: [ *cond,0,0,0,1,0,1,0,1,*Rn_4,(0),(0),(0),(0),*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'CMP<c> <Rn>, <Rm>, <type> <Rs>'
semantic: []
mode: A1
attribute: [ 'cond' ]
encoding: [ *cond,0,0,0,1,0,1,0,1,*Rn_4,(0),(0),(0),(0),*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv7', 'ARMv6T2)']
format: 'DBG<c> #<option>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,1,1,1,0,0,1,1,1,0,1,0,(1),(1),(1),(1),1,0,(0),0,(0),0,0,0,1,1,1,1,*option ]
- processor: ['ARMv7', 'ARMv6Kand', 'ARMv6T2)']
format: 'DBG<c> #<option>'
semantic: []
mode: A1
attribute: []
encoding: [ *cond,0,0,1,1,0,0,1,0,0,0,0,0,(1),(1),(1),(1),(0),(0),(0),(0),1,1,1,1,*option ]
- processor: ['ARMv7']
format: 'DMB<c> #<option>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,1,1,1,0,0,1,1,1,0,1,1,(1),(1),(1),(1),1,0,(0),0,(1),(1),(1),(1),0,1,0,1,*option ]
- processor: ['ARMv7']
format: 'DMB #<option>'
semantic: []
mode: A1
attribute: []
encoding: [ 1,1,1,1,0,1,0,1,0,1,1,1,(1),(1),(1),(1),(1),(1),(1),(1),(0),(0),(0),(0),0,1,0,1,*option ]
- processor: ['ARMv7']
format: 'DSB<c> #<option>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,1,1,1,0,0,1,1,1,0,1,1,(1),(1),(1),(1),1,0,(0),0,(1),(1),(1),(1),0,1,0,0,*option ]
- processor: ['ARMv7']
format: 'DSB #<option>'
semantic: []
mode: A1
attribute: []
encoding: [ 1,1,1,1,0,1,0,1,0,1,1,1,(1),(1),(1),(1),(1),(1),(1),(1),(0),(0),(0),(0),0,1,0,0,*option ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'EOR{S}<c> <Rd>, <Rn>, #<imm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,1,0,*imm_1,0,0,1,0,0,*S,*Rn_4,0,*imm_3,*Rd_4,*imm_8 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'EOR{S}<c> <Rd>, <Rn>, #<arm_expand_imm_c>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,1,0,0,0,1,*S,*Rn_4,*Rd_4,*imm_12 ]
- processor: ['ARMv4T', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'EORS <Rdn>, <Rm>'
semantic: []
mode: T1
attribute: [ 'could_jmp' ]
encoding: [ 0,1,0,0,0,0,0,0,0,1,*Rm_3,*Rdn_3 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'EOR{S}<c>.W <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: T2
attribute: [ 'could_jmp' ]
encoding: [ 1,1,1,0,1,0,1,0,1,0,0,*S,*Rn_4,(0),*imm_3,*Rd_4,*imm_2,*type_2,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'EOR{S}<c> <Rd>, <Rn>, <Rm>{,<shift>}'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,0,0,1,*S,*Rn_4,*Rd_4,*imm_5,*type_2,0,*Rm_4 ]
- processor: ['ARMv4*', 'ARMv5T*', 'ARMv6*', 'ARMv7']
format: 'EOR{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>'
semantic: []
mode: A1
attribute: [ 'could_jmp' ]
encoding: [ *cond,0,0,0,0,0,0,1,*S,*Rn_4,*Rd_4,*Rs_4,0,*type_2,1,*Rm_4 ]
- processor: ['ARMv7']
format: 'ISB<c> #<option>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,1,1,1,0,0,1,1,1,0,1,1,(1),(1),(1),(1),1,0,(0),0,(1),(1),(1),(1),0,1,1,0,*option ]
- processor: ['ARMv7']
format: 'ISB #<option>'
semantic: []
mode: A1
attribute: []
encoding: [ 1,1,1,1,0,1,0,1,0,1,1,1,(1),(1),(1),(1),(1),(1),(1),(1),(0),(0),(0),(0),0,1,1,0,*option ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'IT{x{y{z}}} <firstcond>'
semantic: []
mode: T1
attribute: []
encoding: [ 1,0,1,1,1,1,1,1,*firstcond,*mask_4 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!}'
semantic: []
mode: T1
attribute: ['support_it_block']
encoding: [ 1,1,1,0,1,1,0,*P,*U,*D,*W,1,*Rn_4,*CRd_4,*coproc,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'LDC{L}<c> <coproc>, <CRd>, [<Rn>],<option>'
semantic: []
mode: A1
attribute: ['support_it_block', 'support_it_block']
encoding: [ *cond,1,1,0,*P,*U,*D,*W,1,*Rn_4,*CRd_4,*coproc,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!}'
semantic: []
mode: T2
attribute: ['support_it_block']
encoding: [ 1,1,1,1,1,1,0,*P,*U,*D,*W,1,*Rn_4,*CRd_4,*coproc,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'LDC2{L}<c> <coproc>, <CRd>, [<Rn>],<option>'
semantic: []
mode: A2
attribute: ['support_it_block', 'support_it_block']
encoding: [ 1,1,1,1,1,1,0,*P,*U,*D,*W,1,*Rn_4,*CRd_4,*coproc,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'LDC{L}<c> <coproc>, <CRd>, <label>'
semantic: []
mode: T1
attribute: ['support_it_block']
encoding: [ 1,1,1,0,1,1,0,*P,*U,*D,*W,1,1,1,1,1,*CRd_4,*coproc,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']
format: 'LDC{L}<c> <coproc>, <CRd>, [PC],<option>'
semantic: []
mode: A1
attribute: ['support_it_block', 'support_it_block']
encoding: [ *cond,1,1,0,*P,*U,*D,*W,1,1,1,1,1,*CRd_4,*coproc,*imm_8 ]
- processor: ['ARMv6T2', 'ARMv7']