FIX: Complex Verilog modules always output zeros #43
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Added treating CXXRTL_OUTLINE objects as outputs and it also requires calling outline->eval() to update their values (available from curr[]).
shaos
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Added treating CXXRTL_OUTLINE objects as outputs and it also required calling outline->eval() to update their values to be read from curr[]
Tested it locally with
Yosys 0.21+18 (git sha1 fcd1be142, clang 10.0.0-4ubuntu1 -fPIC -Os)
Wokwi circuit to validate:
https://wokwi.com/projects/366564630633368577