Merge e4d153c into d5670fe

workcraft · Jan 2, 2024 · d001785 · d001785
2 parents d5670fe + e4d153c
commit d001785
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Showing 16 changed files with 124 additions and 70 deletions.
diff --git a/ci/export-circuit/vme-assign.circuit.v.ref b/ci/export-circuit/vme-assign.circuit.v.ref
@@ -0,0 +1,31 @@
+// Verilog netlist generated by Workcraft 3
+module vme (dsr, dsw, ldtack, d, lds, dtack);
+    input dsr, dsw, ldtack;
+    output d, lds, dtack;
+    wire U1_ON, IN_BUBBLE3_ON, IN_BUBBLE5_ON, U7_ON, IN_BUBBLE10_ON, OUT_BUBBLE1_ON, U14_ON, IN_BUBBLE16_ON, IN_BUBBLE18_ON, U20_ON, IN_BUBBLE23_ON, IN_BUBBLE25_ON, IN_BUBBLE28_ON, OUT_BUBBLE2_ON, U31_ON, IN_BUBBLE33_ON, OUT_BUBBLE3_ON, U36_ON;
+
+    assign #1 U1_ON = ~(~OUT_BUBBLE3_ON & ldtack & dsr);
+    assign IN_BUBBLE3_ON = ~OUT_BUBBLE2_ON;
+    assign IN_BUBBLE5_ON = ~ldtack;
+    assign #1 U7_ON = ~((IN_BUBBLE3_ON | d) & (IN_BUBBLE5_ON | OUT_BUBBLE3_ON) & dsw);
+    assign #1 d = ~(U7_ON & U1_ON);
+    assign IN_BUBBLE10_ON = ~OUT_BUBBLE3_ON;
+    assign #1 OUT_BUBBLE1_ON = ~U14_ON;
+    assign #1 U14_ON = ~((d | dsr) & (dsr | OUT_BUBBLE2_ON) & IN_BUBBLE10_ON);
+    assign IN_BUBBLE16_ON = ~OUT_BUBBLE2_ON;
+    assign IN_BUBBLE18_ON = ~dsw;
+    assign #1 U20_ON = ~(OUT_BUBBLE3_ON & (IN_BUBBLE18_ON | IN_BUBBLE16_ON | d));
+    assign #1 lds = U20_ON & OUT_BUBBLE1_ON | lds & (U20_ON | OUT_BUBBLE1_ON);
+    assign IN_BUBBLE23_ON = ~OUT_BUBBLE3_ON;
+    assign IN_BUBBLE25_ON = ~OUT_BUBBLE2_ON;
+    assign #1 dtack = ~(IN_BUBBLE23_ON & dsw | d & OUT_BUBBLE3_ON | IN_BUBBLE25_ON);
+    assign IN_BUBBLE28_ON = ~OUT_BUBBLE3_ON;
+    assign #1 OUT_BUBBLE2_ON = ~U31_ON;
+    assign #1 U31_ON = ~((IN_BUBBLE28_ON | dsw) & (OUT_BUBBLE2_ON | d) & (d | lds));
+    assign IN_BUBBLE33_ON = ~d;
+    assign #1 OUT_BUBBLE3_ON = ~U36_ON;
+    assign #1 U36_ON = ~(IN_BUBBLE33_ON & ldtack & OUT_BUBBLE2_ON | ldtack & OUT_BUBBLE3_ON);
+
+    // signal values at the initial state:
+    // IN_BUBBLE10_ON IN_BUBBLE16_ON IN_BUBBLE18_ON IN_BUBBLE23_ON IN_BUBBLE25_ON IN_BUBBLE28_ON IN_BUBBLE33_ON IN_BUBBLE3_ON IN_BUBBLE5_ON !OUT_BUBBLE1_ON !OUT_BUBBLE2_ON !OUT_BUBBLE3_ON U14_ON U1_ON U20_ON U31_ON U36_ON U7_ON !d !dsr !dsw !dtack !lds !ldtack
+endmodule
diff --git a/ci/export-circuit/vme-tm.circuit.js b/ci/export-circuit/vme-tm.circuit.js
@@ -3,6 +3,7 @@ setConfigVar("CommonEditorSettings.exportHeaderStyle", "BRIEF");
 we = load("vme-tm.circuit.work");
 
 exportCircuitVerilog(we, "vme-tm.circuit.v");
+exportCircuitVerilogAssign(we, "vme-assign.circuit.v");
 
 exportSvg(we, "vme-tm.circuit.svg");
 exportPng(we, "vme-tm.circuit.png");

diff --git a/workcraft/CircuitPlugin/res/scripts/circuit-file.js b/workcraft/CircuitPlugin/res/scripts/circuit-file.js
@@ -15,7 +15,18 @@ framework.addJavaScriptHelp("exportCircuitVerilog", "work, vFileName",
 
 function exportCircuitVerilog(work, vFileName) {
     if (!vFileName.endsWith(".v")) {
-        throw("Verilog netlist file '" + vFileName + "' has incorrect extension, as '.v' is expected");
+        throw("Verilog file '" + vFileName + "' has incorrect extension, as '.v' is expected");
     }
     framework.exportWork(work, vFileName, 'VERILOG');
 }
+
+
+framework.addJavaScriptHelp("exportCircuitVerilogAssigns", "work, vFileName",
+    "export the Circuit 'work' as a Verilog assigns (*.v) file 'vFileName'");
+
+function exportCircuitVerilogAssign(work, vFileName) {
+    if (!vFileName.endsWith(".v")) {
+        throw("Verilog file '" + vFileName + "' has incorrect extension, as '.v' is expected");
+    }
+    framework.exportWork(work, vFileName, 'VERILOG ASSIGNS');
+}
diff --git a/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/CircuitPlugin.java b/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/CircuitPlugin.java
@@ -7,8 +7,9 @@
 import org.workcraft.plugins.PluginManager;
 import org.workcraft.plugins.circuit.commands.*;
 import org.workcraft.plugins.circuit.interop.GenlibImporter;
-import org.workcraft.plugins.circuit.interop.VerilogExporter;
+import org.workcraft.plugins.circuit.interop.VerilogAssignExporter;
 import org.workcraft.plugins.circuit.interop.VerilogImporter;
+import org.workcraft.plugins.circuit.interop.VerilogNetlistExporter;
 import org.workcraft.plugins.circuit.serialisation.FunctionDeserialiser;
 import org.workcraft.plugins.circuit.serialisation.FunctionSerialiser;
 import org.workcraft.utils.ScriptableCommandUtils;
@@ -35,7 +36,8 @@ private void initPluginManager() {
         pm.registerXmlDeserialiser(FunctionDeserialiser.class);
         pm.registerSettings(CircuitSettings.class);
 
-        pm.registerExporter(VerilogExporter.class);
+        pm.registerExporter(VerilogNetlistExporter.class);
+        pm.registerExporter(VerilogAssignExporter.class);
         pm.registerImporter(VerilogImporter.class);
         pm.registerImporter(GenlibImporter.class);
 

diff --git a/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/CircuitSettings.java b/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/CircuitSettings.java
@@ -91,7 +91,6 @@ public class CircuitSettings extends AbstractModelSettings {
     private static final String keyInvertExportSubstitutionRules = prefix + ".invertExportSubstitutionRules";
     private static final String keyImportSubstitutionLibrary = prefix + ".importSubstitutionLibrary";
     private static final String keyInvertImportSubstitutionRules = prefix + ".invertImportSubstitutionRules";
-    private static final String keyExportMappedGatesAsAssign = prefix + ".exportMappedGatesAsAssign";
     private static final String keyVerilogAssignDelay = prefix + ".verilogAssignDelay";
     private static final String keyBusSuffix = prefix + ".busSuffix";
     private static final String keyDissolveSingletonBus = prefix + ".dissolveSingletonBus";
@@ -144,7 +143,6 @@ public class CircuitSettings extends AbstractModelSettings {
     private static final boolean defaultInvertExportSubstitutionRules = false;
     private static final String defaultImportSubstitutionLibrary = "";
     private static final boolean defaultInvertImportSubstitutionRules = true;
-    private static final boolean defaultExportMappedGatesAsAssign = false;
     private static final String defaultVerilogAssignDelay = "1";
     private static final String defaultBusSuffix = "__" + BUS_INDEX_PLACEHOLDER;
     private static final boolean defaultDissolveSingletonBus = true;
@@ -197,7 +195,6 @@ public class CircuitSettings extends AbstractModelSettings {
     private static boolean invertExportSubstitutionRules = defaultInvertExportSubstitutionRules;
     private static String importSubstitutionLibrary = defaultImportSubstitutionLibrary;
     private static boolean invertImportSubstitutionRules = defaultInvertImportSubstitutionRules;
-    private static boolean exportMappedGatesAsAssign = defaultExportMappedGatesAsAssign;
     private static String verilogAssignDelay = defaultVerilogAssignDelay;
     private static String busSuffix = defaultBusSuffix;
     private static boolean dissolveSingletonBus = defaultDissolveSingletonBus;
@@ -347,11 +344,6 @@ public class CircuitSettings extends AbstractModelSettings {
                 CircuitSettings::setInvertImportSubstitutionRules,
                 CircuitSettings::getInvertImportSubstitutionRules));
 
-        properties.add(new PropertyDeclaration<>(Boolean.class,
-                PropertyHelper.BULLET_PREFIX + "Export mapped gates as assign statements",
-                CircuitSettings::setExportMappedGatesAsAssign,
-                CircuitSettings::getExportMappedGatesAsAssign));
-
         properties.add(new PropertyDeclaration<>(String.class,
                 PropertyHelper.BULLET_PREFIX + "Delay for assign statements in Verilog export (empty to suppress)",
                 CircuitSettings::setVerilogAssignDelay,
@@ -541,7 +533,6 @@ public void load(Config config) {
         setInvertExportSubstitutionRules(config.getBoolean(keyInvertExportSubstitutionRules, defaultInvertExportSubstitutionRules));
         setImportSubstitutionLibrary(config.getString(keyImportSubstitutionLibrary, defaultImportSubstitutionLibrary));
         setInvertImportSubstitutionRules(config.getBoolean(keyInvertImportSubstitutionRules, defaultInvertImportSubstitutionRules));
-        setExportMappedGatesAsAssign(config.getBoolean(keyExportMappedGatesAsAssign, defaultExportMappedGatesAsAssign));
         setVerilogAssignDelay(config.getString(keyVerilogAssignDelay, defaultVerilogAssignDelay));
         setBusSuffix(config.getString(keyBusSuffix, defaultBusSuffix));
         setDissolveSingletonBus(config.getBoolean(keyDissolveSingletonBus, defaultDissolveSingletonBus));
@@ -594,7 +585,6 @@ public void save(Config config) {
         config.setBoolean(keyInvertExportSubstitutionRules, getInvertExportSubstitutionRules());
         config.set(keyImportSubstitutionLibrary, getImportSubstitutionLibrary());
         config.setBoolean(keyInvertImportSubstitutionRules, getInvertImportSubstitutionRules());
-        config.setBoolean(keyExportMappedGatesAsAssign, getExportMappedGatesAsAssign());
         config.set(keyVerilogAssignDelay, getVerilogAssignDelay());
         config.set(keyBusSuffix, getBusSuffix());
         config.setBoolean(keyDissolveSingletonBus, getDissolveSingletonBus());
@@ -777,14 +767,6 @@ public static void setInvertImportSubstitutionRules(boolean value) {
         invertImportSubstitutionRules = value;
     }
 
-    public static boolean getExportMappedGatesAsAssign() {
-        return exportMappedGatesAsAssign;
-    }
-
-    public static void setExportMappedGatesAsAssign(boolean value) {
-        exportMappedGatesAsAssign = value;
-    }
-
     public static String getVerilogAssignDelay() {
         return verilogAssignDelay;
     }

diff --git a/...gins/circuit/interop/VerilogExporter.java → ...cuit/interop/AbstractVerilogExporter.java b/...gins/circuit/interop/VerilogExporter.java → ...cuit/interop/AbstractVerilogExporter.java
@@ -28,7 +28,7 @@
 import java.util.regex.Pattern;
 import java.util.stream.Collectors;
 
-public class VerilogExporter implements Exporter {
+public abstract class AbstractVerilogExporter implements Exporter {
 
     private static final String KEYWORD_INPUT = "input";
     private static final String KEYWORD_OUTPUT = "output";
@@ -41,9 +41,7 @@ public class VerilogExporter implements Exporter {
     private final Queue<Pair<File, Circuit>> refinementCircuits = new LinkedList<>();
 
     @Override
-    public VerilogFormat getFormat() {
-        return VerilogFormat.getInstance();
-    }
+    public abstract VerilogFormat getFormat();
 
     @Override
     public boolean isCompatible(Model model) {
@@ -57,8 +55,7 @@ public void serialise(Model model, OutputStream out) {
             Circuit circuit = (Circuit) model;
             String moduleName = ExportUtils.getTitleAsIdentifier(circuit.getTitle());
             File file = getCurrentFile();
-            VerilogFormat format = VerilogFormat.getInstance();
-            writer.write(ExportUtils.getExportHeader("Verilog netlist", "//", moduleName, file, format));
+            writer.write(ExportUtils.getExportHeader("Verilog netlist", "//", moduleName, file, getFormat()));
             refinementCircuits.clear();
             writeCircuit(writer, circuit, moduleName);
             writeRefinementCircuits(writer);
@@ -77,7 +74,7 @@ private void writeCircuit(PrintWriter writer, Circuit circuit, String moduleName
         }
         CircuitSignalInfo circuitInfo = new CircuitSignalInfo(circuit);
         writeHeader(writer, circuitInfo, moduleName);
-        writeInstances(writer, circuitInfo);
+        writeInstances(writer, circuitInfo, getFormat());
         writeInitialState(writer, circuitInfo);
         writer.write(KEYWORD_ENDMODULE);
         writer.write('\n');
@@ -215,8 +212,8 @@ private void writeSignalDefinitions(PrintWriter writer, String keyword, Set<Stri
         }
     }
 
-    private void writeInstances(PrintWriter writer, CircuitSignalInfo circuitInfo) {
-        boolean useAssignments = CircuitSettings.getExportMappedGatesAsAssign();
+    private void writeInstances(PrintWriter writer, CircuitSignalInfo circuitInfo, VerilogFormat format) {
+        boolean useAssignments = format.useAssignOnly();
         // Write assign statements
         boolean hasAssignments = false;
         for (FunctionComponent component : circuitInfo.getCircuit().getFunctionComponents()) {

diff --git a/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogAssignExporter.java b/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogAssignExporter.java
@@ -0,0 +1,10 @@
+package org.workcraft.plugins.circuit.interop;
+
+public class VerilogAssignExporter extends AbstractVerilogExporter {
+
+    @Override
+    public VerilogFormat getFormat() {
+        return VerilogFormat.ASSIGN_STATEMENTS;
+    }
+
+}
diff --git a/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogFormat.java b/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogFormat.java
@@ -1,31 +1,41 @@
 package org.workcraft.plugins.circuit.interop;
 
+import org.workcraft.interop.Format;
+
 import java.util.UUID;
 
-import org.workcraft.interop.Format;
+public enum VerilogFormat implements Format {
 
-public final class VerilogFormat implements Format {
+    DEFAULT("fdd4414e-fd02-4702-b143-09b24430fdd1",
+            "Verilog",
+            "Verilog netlist",
+            false),
 
-    private static VerilogFormat instance = null;
+    ASSIGN_STATEMENTS("f88c58f1-5be6-4d78-96d5-1f6581cac4ec",
+            "Verilog assigns",
+            "Verilog netlist using assign statements",
+            true);
 
-    private VerilogFormat() {
-    }
+    private final UUID uuid;
+    private final String name;
+    private final String description;
+    private final boolean assignOnly;
 
-    public static VerilogFormat getInstance() {
-        if (instance == null) {
-            instance = new VerilogFormat();
-        }
-        return instance;
+    VerilogFormat(String uuidString, String name, String description, boolean assignOnly) {
+        uuid = UUID.fromString(uuidString);
+        this.name = name;
+        this.description = description;
+        this.assignOnly = assignOnly;
     }
 
     @Override
     public UUID getUuid() {
-        return UUID.fromString("fdd4414e-fd02-4702-b143-09b24430fdd1");
+        return uuid;
     }
 
     @Override
     public String getName() {
-        return "Verilog";
+        return name;
     }
 
     @Override
@@ -35,7 +45,11 @@ public String getExtension() {
 
     @Override
     public String getDescription() {
-        return "Verilog netlist";
+        return description;
+    }
+
+    public boolean useAssignOnly() {
+        return assignOnly;
     }
 
 }
diff --git a/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogImporter.java b/workcraft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogImporter.java
@@ -84,7 +84,7 @@ public VerilogImporter(boolean celementAssign, boolean sequentialAssign) {
 
     @Override
     public VerilogFormat getFormat() {
-        return VerilogFormat.getInstance();
+        return VerilogFormat.DEFAULT;
     }
 
     @Override

diff --git a/...craft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogNetlistExporter.java b/...craft/CircuitPlugin/src/org/workcraft/plugins/circuit/interop/VerilogNetlistExporter.java
@@ -0,0 +1,10 @@
+package org.workcraft.plugins.circuit.interop;
+
+public class VerilogNetlistExporter extends AbstractVerilogExporter {
+
+    @Override
+    public VerilogFormat getFormat() {
+        return VerilogFormat.DEFAULT;
+    }
+
+}
diff --git a/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/CircuitSettingsTests.java b/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/CircuitSettingsTests.java
@@ -76,9 +76,6 @@ void circuitSettingsTest() {
         Assertions.assertEquals(Config.toString(CircuitSettings.getInvertImportSubstitutionRules()),
                 framework.getConfigVar(prefix + ".invertImportSubstitutionRules", false));
 
-        Assertions.assertEquals(Config.toString(CircuitSettings.getExportMappedGatesAsAssign()),
-                framework.getConfigVar(prefix + ".exportMappedGatesAsAssign", false));
-
         Assertions.assertEquals(Config.toString(CircuitSettings.getVerilogAssignDelay()),
                 framework.getConfigVar(prefix + ".verilogAssignDelay", false));
 

diff --git a/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/ExportTests.java b/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/ExportTests.java
@@ -29,11 +29,10 @@ static void init() {
 
     @Test
     void testBufferExport() throws DeserialisationException, IOException, SerialisationException {
-        String vHeader = String.format(
-                "// Verilog netlist generated by Workcraft 3\n" +
-                        "module buffer (in, out);\n" +
-                        "    input in;\n" +
-                        "    output out;\n");
+        String vHeader = "// Verilog netlist generated by Workcraft 3\n" +
+                "module buffer (in, out);\n" +
+                "    input in;\n" +
+                "    output out;\n";
 
         String svgHeader = String.format(
                 "<?xml version=\"1.0\" encoding=\"UTF-8\"?>%n" +
@@ -64,7 +63,7 @@ private void testExport(String workName, String vHeader,
         File directory = FileUtils.createTempDirectory(FileUtils.getTempPrefix(workName));
 
         File vFile = new File(directory, "export.v");
-        framework.exportModel(me, vFile, VerilogFormat.getInstance());
+        framework.exportModel(me, vFile, VerilogFormat.DEFAULT);
         Assertions.assertEquals(vHeader, FileUtils.readHeaderUtf8(vFile, vHeader.length()));
 
         File svgFile = new File(directory, "export.svg");

diff --git a/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/ImportExportTests.java b/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/ImportExportTests.java
@@ -137,7 +137,7 @@ private void testImportExport(String workName, String verilogName) throws Deseri
         try {
             File vFile = File.createTempFile("workcraft-", ".v");
             vFile.deleteOnExit();
-            framework.exportWork(wWe, vFile, VerilogFormat.getInstance());
+            framework.exportWork(wWe, vFile, VerilogFormat.DEFAULT);
             vWe = framework.importWork(vFile);
             collectNodes(vWe, vInputs, vOutputs, vGates);
         } catch (IOException | SerialisationException e) {

diff --git a/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/ImportHierarchyTests.java b/workcraft/CircuitPlugin/test-src/org/workcraft/plugins/circuit/ImportHierarchyTests.java
@@ -57,7 +57,7 @@ private void testImportExport(String fileName, String topModuleName, Set<String>
         Assertions.assertEquals(expectedFileNames, actualFileNames);
 
         File vOutFile = new File(tmpDirectory, fileName);
-        framework.exportWork(we, vOutFile, VerilogFormat.getInstance());
+        framework.exportWork(we, vOutFile, VerilogFormat.DEFAULT);
 
         String expectedVerilog = FileUtils.readAllText(vFile);
         String actualVerilog = FileUtils.readAllText(vOutFile);