RV32I_piped

WIP pipelined implementation of the RISC-V RV32I instruction set architecture.

Current Instruction Support

• R-Type: ADD/SUB/XOR/OR/AND/SLT/SLTU/SLL/SRL/SRA.

Current Modules

• Instruction Decoder

• Register File

• Arithmetic Logic Unit

• Finite State Machine

Testbench Status

• Barebone SystsemVerilog unit.

• Parameters manually declared before compilation.

Immediate Next Steps

• Support I-type instructions.

• Clean up and expand testbench.