Convert all Intel 440BX boards to Cache-as-RAM (CAR).

 - Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.

 - Add the following in src/cpu/intel/slot_1/Makefile.inc:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Remove "select ROMCC" from all 440BX board Kconfig files.

 - Drop all early_mtrr_init() calls, that's done by CAR code now.

Various small fixes were needed to make it build:

 - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
   those were never called anyways.

 - Remove the "static" from the main() functions in romstage.c files.

 - Always call dump_spd_registers() from the 440BX debug.c, but use
   "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
   is enabled in menuconfig.

 - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
   commented out) from romstage.c's, as we've done for most other boards.

 - Add missing #includes or prototypes. Some of the prototypes will be
   removed later when we get rid of the #include'd .c files.

Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/intel/slot_1/Kconfig

@@ -19,6 +19,7 @@
 
 config CPU_INTEL_SLOT_1
 	bool
+	select CACHE_AS_RAM
 
 config DCACHE_RAM_BASE
 	hex

src/cpu/intel/slot_1/Makefile.inc

@@ -27,3 +27,5 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+

src/mainboard/a-trend/atc-6220/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256

src/mainboard/a-trend/atc-6220/romstage.c

@@ -26,16 +26,15 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0)
-		early_mtrr_init();
-
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/a-trend/atc-6240/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83627HF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256

src/mainboard/a-trend/atc-6240/romstage.c

@@ -26,16 +26,15 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
 
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0)
-		early_mtrr_init();
-
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/abit/be6-ii_v2_0/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256

src/mainboard/abit/be6-ii_v2_0/romstage.c

@@ -26,17 +26,16 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 /* FIXME: It's a Winbond W83977EF, actually. */
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
 
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -49,11 +48,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0)
-		early_mtrr_init();
-
 	/* FIXME: It's a Winbond W83977EF, actually. */
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/asus/p2b-d/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select SMP

src/mainboard/asus/p2b-d/romstage.c

@@ -27,16 +27,15 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
@@ -48,12 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0) {
-		early_mtrr_init();
-		enable_lapic();		/* FIXME? */
-	}
+	enable_lapic();		/* FIXME? */
 
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/asus/p2b-ds/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select SMP

src/mainboard/asus/p2b-ds/romstage.c

@@ -27,16 +27,15 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
@@ -48,12 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0) {
-		early_mtrr_init();
-		enable_lapic();		/* FIXME? */
-	}
+	enable_lapic();		/* FIXME? */
 
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/asus/p2b-f/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256

src/mainboard/asus/p2b-f/romstage.c

@@ -26,17 +26,16 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
 
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -49,11 +48,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0)
-		early_mtrr_init();
-
 	/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/asus/p2b-ls/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256

src/mainboard/asus/p2b-ls/romstage.c

@@ -26,17 +26,16 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
@@ -48,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	if (bist == 0)
-		early_mtrr_init();
-
 	/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
@@ -63,10 +59,8 @@ static void main(unsigned long bist)
 	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
 
 	enable_smbus();
-	/* dump_spd_registers(); */
+	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
 	sdram_enable();
-	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/asus/p2b/Kconfig

@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I440BX
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select SUPERIO_WINBOND_W83977TF
-	select ROMCC
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256