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Bug Fixes
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@wwarthen
wwarthen committed Feb 21, 2021
1 parent 78b6686 commit a1a2546
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Showing 14 changed files with 107 additions and 97 deletions.
33 changes: 27 additions & 6 deletions Source/Apps/RTC.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,11 @@ PORT_N8 .EQU $88 ; RTC port for N8
PORT_MK4 .EQU $8A ; RTC port for MK4
PORT_RCZ80 .EQU $C0 ; RTC port for RC2014
PORT_RCZ180 .EQU $0C ; RTC port for RC2014
PORT_SCZ180 .EQU $0C ; RTC port for SBCZ180
PORT_EZZ80 .EQU $C0 ; RTC port for EZZ80 (actually does not have one!!!)
PORT_SCZ180 .EQU $0C ; RTC port for SCZ180
PORT_DYNO .EQU $0C ; RTC port for DYNO
PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280


BDOS .EQU 5 ; BDOS invocation vector
FCB .EQU 05CH ; Start of command line
Expand Down Expand Up @@ -1075,30 +1078,46 @@ HINIT:
JR Z,RTC_INIT2
CP $03 ; ZETA 2
JR Z,RTC_INIT2
;
LD C,PORT_N8
LD DE,PLT_N8
CP $04 ; N8
JR Z,RTC_INIT2
;
LD C,PORT_MK4
LD DE,PLT_MK4
CP $05 ; Mark IV
JR Z,RTC_INIT2
;
LD C,PORT_RCZ80
LD DE,PLT_RCZ80
CP $07 ; RC2014 w/ Z80
JR Z,RTC_INIT2
;
LD C,PORT_RCZ180
LD DE,PLT_RCZ180
CP $08 ; RC2014 w/ Z180
JR Z,RTC_INIT2
;
LD C,PORT_EZZ80
LD DE,PLT_EZZ80
CP $09 ; Easy Z80
JR Z,RTC_INIT2
;
LD C,PORT_SCZ180
LD DE,PLT_SCZ180
CP $0A ; SCZ180
JR Z,RTC_INIT2
;LD C,PORT_EZZ80
;LD DE,PLT_EZZ80
;CP $09 ; Easy Z80
;JR Z,RTC_INIT2
;
LD C,PORT_DYNO
LD DE,PLT_DYNO
CP 11 ; DYNO
JR Z,RTC_INIT2
;
LD C,PORT_RCZ280
LD DE,PLT_RCZ280
CP 12 ; RCZ280
JR Z,RTC_INIT2
;
; Unknown platform
LD DE,PLTERR ; BIOS error message
Expand Down Expand Up @@ -1719,8 +1738,10 @@ PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$"
PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$"
PLT_RCZ80 .TEXT ", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_RCZ180 .TEXT ", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_EZZ80 .TEXT ", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_DYNO .TEXT ", DYNO RTC Module Latch Port 0x0C\r\n$"
PLT_RCZ280 .TEXT ", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"

;
; Generic FOR-NEXT loop algorithm
Expand Down
17 changes: 11 additions & 6 deletions Source/Apps/Tune/Tune.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,8 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file
;
; HIGH SPEED CPU CONTROL
;
SBCV2004 .EQU 0 ; USE SBC-V2-004 HALF CLOCK DIVIDER
CPUFAMZ180 .EQU 1 ; USE Z180 WAIT STATE MANAGEMENT
SBCV2004 .EQU 0 ; ENABLE SBC-V2-004 HALF CLOCK DIVIDER
CPUFAMZ180 .EQU 1 ; ENABLE Z180 WAIT STATE MANAGEMENT
;
;Conditional assembly - use -D switch on TASM or uz80as assembler to control
_ZX .EQU 0 ; 1) Version of ROUT (ZX or MSX standards)
Expand Down Expand Up @@ -596,6 +596,15 @@ CFGTBL: ; PLT RSEL RDAT RIN Z180 ACR
;
.DB $0A, $61, $60, $60, $C0, $FF ; SCZ180 W/ RC SOUND MODULE (MF)
.DW HWSTR_RCMF
;
.DB $0B, $D8, $D0, $D8, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB
;
.DB $0B, $A0, $A1, $A2, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB Rev 6)
.DW HWSTR_RCEB6
;
.DB $0B, $D1, $D0, $D0, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (MF)
.DW HWSTR_RCMF
;
.DB $FF ; END OF TABLE MARKER
;
Expand Down Expand Up @@ -2478,10 +2487,6 @@ upsg:
ERRWITHMSG(MSGERR)

upsg0:
ld a,(WMOD) ; if WMOD = 1, CPU is z180
or a ; set flags
jr z,upsg1 ; skip z180 stuff

di
call SLOWIO

Expand Down
3 changes: 2 additions & 1 deletion Source/HBIOS/Config/RCZ280_nat_zz.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -26,4 +26,5 @@
;
#include "Config/RCZ280_nat.asm"
;
RAMLOC .SET 23 ; START OF RAM AS POWER OF 2 (2^N)
RAMLOC .SET 23 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .SET (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
2 changes: 1 addition & 1 deletion Source/HBIOS/cfg_dyno.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
Expand Down
2 changes: 1 addition & 1 deletion Source/HBIOS/cfg_master.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,8 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .SET MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
Expand Down
2 changes: 1 addition & 1 deletion Source/HBIOS/cfg_mk4.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Expand Down
2 changes: 1 addition & 1 deletion Source/HBIOS/cfg_rcz180.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
Expand Down
2 changes: 1 addition & 1 deletion Source/HBIOS/cfg_rcz280.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
Expand Down
2 changes: 1 addition & 1 deletion Source/HBIOS/cfg_scz180.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Expand Down
16 changes: 10 additions & 6 deletions Source/HBIOS/dbgmon.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ BUFLEN .EQU 40 ; INPUT LINE LENGTH
;
UART_ENTRY:
LD SP,MON_STACK ; SET THE STACK POINTER
EI ; INTS OK NOW
;EI ; INTS OK NOW
LD HL,UART_ENTRY ; RESTART ADDRESS
CALL INITIALIZE ; INITIALIZE SYSTEM

Expand Down Expand Up @@ -132,10 +132,14 @@ INITIALIZE:
LD (9),HL ; STORE AT 0x0009
#ENDIF

;#IF (BIOS == BIOS_WBW)
; CALL DELAY_INIT
;#ENDIF

#IF DSKYENABLE
LD B,BF_SYSGET ; HBIOS FUNC=GET SYS INFO
LD C,BF_SYSGET_CPUINFO ; HBIOS SUBFUNC=GET CPU INFO
RST 08 ; CALL HBIOS
LD A,L ; PUT SPEED IN MHZ IN ACCUM
CALL DELAY_INIT
#ENDIF
;
RET
;
;__BOOT_______________________________________________________________________
Expand Down Expand Up @@ -962,7 +966,7 @@ KY_PW .EQU KY_BK ; USE [BW] FOR [PW] (PORT WRITE)
;
DSKY_ENTRY:
LD SP,MON_STACK ; SET THE STACK POINTER
EI ; INTS OK NOW
;EI ; INTS OK NOW
LD HL,DSKY_ENTRY ; RESTART ADDRESS
CALL INITIALIZE
;
Expand Down

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