Modifed the settings that seem to hardcode the two-lane operation of …

…the MIPI DPHY as reported in https://groups.google.com/d/msg/linux-rockchip/qnX2QlaLM3A/cBvi_kTOAgAJ
wzab · Feb 12, 2020 · 39748a6 · 39748a6
1 parent 712660f
commit 39748a6
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c b/drivers/staging/media/rkisp1/rkisp1-isp.c
@@ -462,7 +462,7 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
 	rkisp1_write(rkisp1,
 		     RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
 		     RKISP1_CIF_MIPI_ERR_DPHY |
-		     RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
+		     RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x01) |
 		     RKISP1_CIF_MIPI_ADD_DATA_OVFLW,
 		     RKISP1_CIF_MIPI_IMSC);
 

diff --git a/drivers/staging/media/rkisp1/rkisp1-regs.h b/drivers/staging/media/rkisp1/rkisp1-regs.h
@@ -335,10 +335,10 @@
 	RKISP1_CIF_MIPI_ERR_ECC2 | \
 	RKISP1_CIF_MIPI_ERR_CS)
 
-#define RKISP1_CIF_MIPI_ERR_DPHY  (RKISP1_CIF_MIPI_ERR_SOT(3) | \
-	RKISP1_CIF_MIPI_ERR_SOT_SYNC(3) | \
-	RKISP1_CIF_MIPI_ERR_EOT_SYNC(3) | \
-	RKISP1_CIF_MIPI_ERR_CTRL(3))
+#define RKISP1_CIF_MIPI_ERR_DPHY  (RKISP1_CIF_MIPI_ERR_SOT(1) | \
+	RKISP1_CIF_MIPI_ERR_SOT_SYNC(1) | \
+	RKISP1_CIF_MIPI_ERR_EOT_SYNC(1) | \
+	RKISP1_CIF_MIPI_ERR_CTRL(1))
 
 /* SUPER_IMPOSE */
 #define RKISP1_CIF_SUPER_IMP_CTRL_NORMAL_MODE		BIT(0)