It seems that the relation between the pixel_rate and link clock freq…

…uency

may be based on number of bits "per sample", not "per pixel".
If that's true, we may need to set bpp for our format to 8 (as it was
originally) and instead increase the "pixel_rate" (which then in fact
is the "byte_rate" from 27MHz to 54MHz.
That commit is implementing those modifications.

drivers/media/i2c/adv7180.c

@@ -635,7 +635,7 @@ static int adv7180_init_controls(struct adv7180_state *state)
 	if (state->link_freq)
 		state->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 	//pixel_rate = mode->vts_def * mode->hts_def * mode->max_fps;
-	pixel_rate = ADV7180_LINK_FREQ_216MHZ * 2 / 16;
+	pixel_rate = ADV7180_LINK_FREQ_216MHZ * 2 / 8;
 	state->pixel_rate = v4l2_ctrl_new_std(&state->ctrl_hdl, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate,
 						1, pixel_rate);
 

drivers/staging/media/rkisp1/rkisp1-isp.c

@@ -181,7 +181,7 @@ static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = {
 		.fmt_type	= RKISP1_FMT_YUV,
 		.mipi_dt	= RKISP1_CIF_CSI2_DT_YUV422_8b,
 		.yuv_seq	= RKISP1_CIF_ISP_ACQ_PROP_CBYCRY,
-		.bus_width	= 16,
+		.bus_width	= 8,
 		.direction	= RKISP1_DIR_SINK,
 	}, {
 		.mbus_code	= MEDIA_BUS_FMT_VYUY8_1X16,