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The HDMI block has a block that controls clocks and reset signals to the HDMI0 and HDMI1 controllers. Let's expose that through a clock driver implementing a clock and reset provider. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/bb60d97fc76b61c2eabef5a02ebd664c0f57ede0.1591867332.git-series.maxime@cerno.tech Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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// SPDX-License-Identifier: GPL-2.0-or-later | ||
// Copyright 2020 Cerno | ||
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#include <linux/clk-provider.h> | ||
#include <linux/module.h> | ||
#include <linux/platform_device.h> | ||
#include <linux/reset-controller.h> | ||
#include <linux/reset/reset-simple.h> | ||
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#define DVP_HT_RPI_SW_INIT 0x04 | ||
#define DVP_HT_RPI_MISC_CONFIG 0x08 | ||
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#define NR_CLOCKS 2 | ||
#define NR_RESETS 6 | ||
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struct clk_dvp { | ||
struct clk_hw_onecell_data *data; | ||
struct reset_simple_data reset; | ||
}; | ||
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static const struct clk_parent_data clk_dvp_parent = { | ||
.index = 0, | ||
}; | ||
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static int clk_dvp_probe(struct platform_device *pdev) | ||
{ | ||
struct clk_hw_onecell_data *data; | ||
struct resource *res; | ||
struct clk_dvp *dvp; | ||
void __iomem *base; | ||
int ret; | ||
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dvp = devm_kzalloc(&pdev->dev, sizeof(*dvp), GFP_KERNEL); | ||
if (!dvp) | ||
return -ENOMEM; | ||
platform_set_drvdata(pdev, dvp); | ||
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dvp->data = devm_kzalloc(&pdev->dev, | ||
struct_size(dvp->data, hws, NR_CLOCKS), | ||
GFP_KERNEL); | ||
if (!dvp->data) | ||
return -ENOMEM; | ||
data = dvp->data; | ||
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); | ||
if (IS_ERR(base)) | ||
return PTR_ERR(base); | ||
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dvp->reset.rcdev.owner = THIS_MODULE; | ||
dvp->reset.rcdev.nr_resets = NR_RESETS; | ||
dvp->reset.rcdev.ops = &reset_simple_ops; | ||
dvp->reset.rcdev.of_node = pdev->dev.of_node; | ||
dvp->reset.membase = base + DVP_HT_RPI_SW_INIT; | ||
spin_lock_init(&dvp->reset.lock); | ||
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ret = devm_reset_controller_register(&pdev->dev, &dvp->reset.rcdev); | ||
if (ret) | ||
return ret; | ||
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data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev, | ||
"hdmi0-108MHz", | ||
&clk_dvp_parent, 0, | ||
base + DVP_HT_RPI_MISC_CONFIG, 3, | ||
CLK_GATE_SET_TO_DISABLE, | ||
&dvp->reset.lock); | ||
if (IS_ERR(data->hws[0])) | ||
return PTR_ERR(data->hws[0]); | ||
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data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev, | ||
"hdmi1-108MHz", | ||
&clk_dvp_parent, 0, | ||
base + DVP_HT_RPI_MISC_CONFIG, 4, | ||
CLK_GATE_SET_TO_DISABLE, | ||
&dvp->reset.lock); | ||
if (IS_ERR(data->hws[1])) { | ||
ret = PTR_ERR(data->hws[1]); | ||
goto unregister_clk0; | ||
} | ||
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data->num = NR_CLOCKS; | ||
ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, | ||
data); | ||
if (ret) | ||
goto unregister_clk1; | ||
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return 0; | ||
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unregister_clk1: | ||
clk_hw_unregister_gate(data->hws[1]); | ||
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unregister_clk0: | ||
clk_hw_unregister_gate(data->hws[0]); | ||
return ret; | ||
}; | ||
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static int clk_dvp_remove(struct platform_device *pdev) | ||
{ | ||
struct clk_dvp *dvp = platform_get_drvdata(pdev); | ||
struct clk_hw_onecell_data *data = dvp->data; | ||
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clk_hw_unregister_gate(data->hws[1]); | ||
clk_hw_unregister_gate(data->hws[0]); | ||
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return 0; | ||
} | ||
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static const struct of_device_id clk_dvp_dt_ids[] = { | ||
{ .compatible = "brcm,brcm2711-dvp", }, | ||
{ /* sentinel */ } | ||
}; | ||
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static struct platform_driver clk_dvp_driver = { | ||
.probe = clk_dvp_probe, | ||
.remove = clk_dvp_remove, | ||
.driver = { | ||
.name = "brcm2711-dvp", | ||
.of_match_table = clk_dvp_dt_ids, | ||
}, | ||
}; | ||
module_platform_driver(clk_dvp_driver); |