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mfd: cs42l43: Fix wrong register defaults
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[ Upstream commit c9e1e505cde1a8ddd0968b4d54ec2ea1937dfe00 ]

A few regs have unnecessary values in defaults, change them to match the
datasheet

Fixes: ace6d14 ("mfd: cs42l43: Add support for cs42l43 core driver")

Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20240229155616.118457-1-mstrozek@opensource.cirrus.com
Signed-off-by: Lee Jones <lee@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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Maciej Strozek authored and Sasha Levin committed Mar 26, 2024
1 parent a3dd12b commit 30d1366
Showing 1 changed file with 34 additions and 34 deletions.
68 changes: 34 additions & 34 deletions drivers/mfd/cs42l43.c
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Expand Up @@ -131,38 +131,38 @@ const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
{ CS42L43_ASP_TX_CH4_CTRL, 0x00170091 },
{ CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 },
{ CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 },
{ CS42L43_ASPTX1_INPUT, 0x00800000 },
{ CS42L43_ASPTX2_INPUT, 0x00800000 },
{ CS42L43_ASPTX3_INPUT, 0x00800000 },
{ CS42L43_ASPTX4_INPUT, 0x00800000 },
{ CS42L43_ASPTX5_INPUT, 0x00800000 },
{ CS42L43_ASPTX6_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH2_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH3_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH4_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP2_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP2_CH2_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP3_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP3_CH2_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP4_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP4_CH2_INPUT, 0x00800000 },
{ CS42L43_ASRC_INT1_INPUT1, 0x00800000 },
{ CS42L43_ASRC_INT2_INPUT1, 0x00800000 },
{ CS42L43_ASRC_INT3_INPUT1, 0x00800000 },
{ CS42L43_ASRC_INT4_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC1_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC2_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC3_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC4_INPUT1, 0x00800000 },
{ CS42L43_ISRC1INT1_INPUT1, 0x00800000 },
{ CS42L43_ISRC1INT2_INPUT1, 0x00800000 },
{ CS42L43_ISRC1DEC1_INPUT1, 0x00800000 },
{ CS42L43_ISRC1DEC2_INPUT1, 0x00800000 },
{ CS42L43_ISRC2INT1_INPUT1, 0x00800000 },
{ CS42L43_ISRC2INT2_INPUT1, 0x00800000 },
{ CS42L43_ISRC2DEC1_INPUT1, 0x00800000 },
{ CS42L43_ISRC2DEC2_INPUT1, 0x00800000 },
{ CS42L43_ASPTX1_INPUT, 0x00000000 },
{ CS42L43_ASPTX2_INPUT, 0x00000000 },
{ CS42L43_ASPTX3_INPUT, 0x00000000 },
{ CS42L43_ASPTX4_INPUT, 0x00000000 },
{ CS42L43_ASPTX5_INPUT, 0x00000000 },
{ CS42L43_ASPTX6_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP1_CH1_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP1_CH2_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP1_CH3_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP1_CH4_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP2_CH1_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 },
{ CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 },
{ CS42L43_ASRC_INT1_INPUT1, 0x00000000 },
{ CS42L43_ASRC_INT2_INPUT1, 0x00000000 },
{ CS42L43_ASRC_INT3_INPUT1, 0x00000000 },
{ CS42L43_ASRC_INT4_INPUT1, 0x00000000 },
{ CS42L43_ASRC_DEC1_INPUT1, 0x00000000 },
{ CS42L43_ASRC_DEC2_INPUT1, 0x00000000 },
{ CS42L43_ASRC_DEC3_INPUT1, 0x00000000 },
{ CS42L43_ASRC_DEC4_INPUT1, 0x00000000 },
{ CS42L43_ISRC1INT1_INPUT1, 0x00000000 },
{ CS42L43_ISRC1INT2_INPUT1, 0x00000000 },
{ CS42L43_ISRC1DEC1_INPUT1, 0x00000000 },
{ CS42L43_ISRC1DEC2_INPUT1, 0x00000000 },
{ CS42L43_ISRC2INT1_INPUT1, 0x00000000 },
{ CS42L43_ISRC2INT2_INPUT1, 0x00000000 },
{ CS42L43_ISRC2DEC1_INPUT1, 0x00000000 },
{ CS42L43_ISRC2DEC2_INPUT1, 0x00000000 },
{ CS42L43_EQ1MIX_INPUT1, 0x00800000 },
{ CS42L43_EQ1MIX_INPUT2, 0x00800000 },
{ CS42L43_EQ1MIX_INPUT3, 0x00800000 },
Expand All @@ -171,8 +171,8 @@ const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
{ CS42L43_EQ2MIX_INPUT2, 0x00800000 },
{ CS42L43_EQ2MIX_INPUT3, 0x00800000 },
{ CS42L43_EQ2MIX_INPUT4, 0x00800000 },
{ CS42L43_SPDIF1_INPUT1, 0x00800000 },
{ CS42L43_SPDIF2_INPUT1, 0x00800000 },
{ CS42L43_SPDIF1_INPUT1, 0x00000000 },
{ CS42L43_SPDIF2_INPUT1, 0x00000000 },
{ CS42L43_AMP1MIX_INPUT1, 0x00800000 },
{ CS42L43_AMP1MIX_INPUT2, 0x00800000 },
{ CS42L43_AMP1MIX_INPUT3, 0x00800000 },
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