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iio: adc: add driver for Rockchip saradc
The ADC is a 3-channel signal-ended 10-bit Successive Approximation Register (SAR) A/D Converter. It uses the supply and ground as its reference and converts the analog input signal into 10-bit binary digital codes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Hartmut Knaack <knaack.h@gmx.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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/* | ||
* Rockchip Successive Approximation Register (SAR) A/D Converter | ||
* Copyright (C) 2014 ROCKCHIP, Inc. | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License as published by | ||
* the Free Software Foundation; either version 2 of the License, or | ||
* (at your option) any later version. | ||
* | ||
* This program is distributed in the hope that it will be useful, | ||
* but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
* GNU General Public License for more details. | ||
*/ | ||
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#include <linux/module.h> | ||
#include <linux/platform_device.h> | ||
#include <linux/interrupt.h> | ||
#include <linux/io.h> | ||
#include <linux/of.h> | ||
#include <linux/clk.h> | ||
#include <linux/completion.h> | ||
#include <linux/regulator/consumer.h> | ||
#include <linux/iio/iio.h> | ||
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#define SARADC_DATA 0x00 | ||
#define SARADC_DATA_MASK 0x3ff | ||
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#define SARADC_STAS 0x04 | ||
#define SARADC_STAS_BUSY BIT(0) | ||
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#define SARADC_CTRL 0x08 | ||
#define SARADC_CTRL_IRQ_STATUS BIT(6) | ||
#define SARADC_CTRL_IRQ_ENABLE BIT(5) | ||
#define SARADC_CTRL_POWER_CTRL BIT(3) | ||
#define SARADC_CTRL_CHN_MASK 0x7 | ||
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#define SARADC_DLY_PU_SOC 0x0c | ||
#define SARADC_DLY_PU_SOC_MASK 0x3f | ||
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#define SARADC_BITS 10 | ||
#define SARADC_TIMEOUT msecs_to_jiffies(100) | ||
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struct rockchip_saradc { | ||
void __iomem *regs; | ||
struct clk *pclk; | ||
struct clk *clk; | ||
struct completion completion; | ||
struct regulator *vref; | ||
u16 last_val; | ||
}; | ||
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static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, | ||
struct iio_chan_spec const *chan, | ||
int *val, int *val2, long mask) | ||
{ | ||
struct rockchip_saradc *info = iio_priv(indio_dev); | ||
int ret; | ||
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switch (mask) { | ||
case IIO_CHAN_INFO_RAW: | ||
mutex_lock(&indio_dev->mlock); | ||
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reinit_completion(&info->completion); | ||
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/* 8 clock periods as delay between power up and start cmd */ | ||
writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); | ||
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/* Select the channel to be used and trigger conversion */ | ||
writel(SARADC_CTRL_POWER_CTRL | ||
| (chan->channel & SARADC_CTRL_CHN_MASK) | ||
| SARADC_CTRL_IRQ_ENABLE, | ||
info->regs + SARADC_CTRL); | ||
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if (!wait_for_completion_timeout(&info->completion, | ||
SARADC_TIMEOUT)) { | ||
writel_relaxed(0, info->regs + SARADC_CTRL); | ||
mutex_unlock(&indio_dev->mlock); | ||
return -ETIMEDOUT; | ||
} | ||
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*val = info->last_val; | ||
mutex_unlock(&indio_dev->mlock); | ||
return IIO_VAL_INT; | ||
case IIO_CHAN_INFO_SCALE: | ||
ret = regulator_get_voltage(info->vref); | ||
if (ret < 0) { | ||
dev_err(&indio_dev->dev, "failed to get voltage\n"); | ||
return ret; | ||
} | ||
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*val = ret / 1000; | ||
*val2 = SARADC_BITS; | ||
return IIO_VAL_FRACTIONAL_LOG2; | ||
default: | ||
return -EINVAL; | ||
} | ||
} | ||
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static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) | ||
{ | ||
struct rockchip_saradc *info = (struct rockchip_saradc *)dev_id; | ||
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/* Read value */ | ||
info->last_val = readl_relaxed(info->regs + SARADC_DATA); | ||
info->last_val &= SARADC_DATA_MASK; | ||
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/* Clear irq & power down adc */ | ||
writel_relaxed(0, info->regs + SARADC_CTRL); | ||
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complete(&info->completion); | ||
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return IRQ_HANDLED; | ||
} | ||
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static const struct iio_info rockchip_saradc_iio_info = { | ||
.read_raw = rockchip_saradc_read_raw, | ||
.driver_module = THIS_MODULE, | ||
}; | ||
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#define ADC_CHANNEL(_index, _id) { \ | ||
.type = IIO_VOLTAGE, \ | ||
.indexed = 1, \ | ||
.channel = _index, \ | ||
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | ||
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ | ||
.datasheet_name = _id, \ | ||
} | ||
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static const struct iio_chan_spec rockchip_saradc_iio_channels[] = { | ||
ADC_CHANNEL(0, "adc0"), | ||
ADC_CHANNEL(1, "adc1"), | ||
ADC_CHANNEL(2, "adc2"), | ||
}; | ||
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static int rockchip_saradc_probe(struct platform_device *pdev) | ||
{ | ||
struct rockchip_saradc *info = NULL; | ||
struct device_node *np = pdev->dev.of_node; | ||
struct iio_dev *indio_dev = NULL; | ||
struct resource *mem; | ||
int ret; | ||
int irq; | ||
u32 rate; | ||
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if (!np) | ||
return -ENODEV; | ||
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); | ||
if (!indio_dev) { | ||
dev_err(&pdev->dev, "failed allocating iio device\n"); | ||
return -ENOMEM; | ||
} | ||
info = iio_priv(indio_dev); | ||
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
info->regs = devm_ioremap_resource(&pdev->dev, mem); | ||
if (IS_ERR(info->regs)) | ||
return PTR_ERR(info->regs); | ||
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init_completion(&info->completion); | ||
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irq = platform_get_irq(pdev, 0); | ||
if (irq < 0) { | ||
dev_err(&pdev->dev, "no irq resource?\n"); | ||
return irq; | ||
} | ||
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ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, | ||
0, dev_name(&pdev->dev), info); | ||
if (ret < 0) { | ||
dev_err(&pdev->dev, "failed requesting irq %d\n", irq); | ||
return ret; | ||
} | ||
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info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | ||
if (IS_ERR(info->pclk)) { | ||
dev_err(&pdev->dev, "failed to get pclk\n"); | ||
return PTR_ERR(info->pclk); | ||
} | ||
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info->clk = devm_clk_get(&pdev->dev, "saradc"); | ||
if (IS_ERR(info->clk)) { | ||
dev_err(&pdev->dev, "failed to get adc clock\n"); | ||
return PTR_ERR(info->clk); | ||
} | ||
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info->vref = devm_regulator_get(&pdev->dev, "vref"); | ||
if (IS_ERR(info->vref)) { | ||
dev_err(&pdev->dev, "failed to get regulator, %ld\n", | ||
PTR_ERR(info->vref)); | ||
return PTR_ERR(info->vref); | ||
} | ||
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/* | ||
* Use a default of 1MHz for the converter clock. | ||
* This may become user-configurable in the future. | ||
*/ | ||
ret = clk_set_rate(info->clk, 1000000); | ||
if (ret < 0) { | ||
dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret); | ||
return ret; | ||
} | ||
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ret = regulator_enable(info->vref); | ||
if (ret < 0) { | ||
dev_err(&pdev->dev, "failed to enable vref regulator\n"); | ||
return ret; | ||
} | ||
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ret = clk_prepare_enable(info->pclk); | ||
if (ret < 0) { | ||
dev_err(&pdev->dev, "failed to enable pclk\n"); | ||
goto err_reg_voltage; | ||
} | ||
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ret = clk_prepare_enable(info->clk); | ||
if (ret < 0) { | ||
dev_err(&pdev->dev, "failed to enable converter clock\n"); | ||
goto err_pclk; | ||
} | ||
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platform_set_drvdata(pdev, indio_dev); | ||
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indio_dev->name = dev_name(&pdev->dev); | ||
indio_dev->dev.parent = &pdev->dev; | ||
indio_dev->dev.of_node = pdev->dev.of_node; | ||
indio_dev->info = &rockchip_saradc_iio_info; | ||
indio_dev->modes = INDIO_DIRECT_MODE; | ||
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indio_dev->channels = rockchip_saradc_iio_channels; | ||
indio_dev->num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels); | ||
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ret = iio_device_register(indio_dev); | ||
if (ret) | ||
goto err_clk; | ||
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return 0; | ||
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err_clk: | ||
clk_disable_unprepare(info->clk); | ||
err_pclk: | ||
clk_disable_unprepare(info->pclk); | ||
err_reg_voltage: | ||
regulator_disable(info->vref); | ||
return ret; | ||
} | ||
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static int rockchip_saradc_remove(struct platform_device *pdev) | ||
{ | ||
struct iio_dev *indio_dev = platform_get_drvdata(pdev); | ||
struct rockchip_saradc *info = iio_priv(indio_dev); | ||
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iio_device_unregister(indio_dev); | ||
clk_disable_unprepare(info->clk); | ||
clk_disable_unprepare(info->pclk); | ||
regulator_disable(info->vref); | ||
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return 0; | ||
} | ||
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#ifdef CONFIG_PM_SLEEP | ||
static int rockchip_saradc_suspend(struct device *dev) | ||
{ | ||
struct iio_dev *indio_dev = dev_get_drvdata(dev); | ||
struct rockchip_saradc *info = iio_priv(indio_dev); | ||
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clk_disable_unprepare(info->clk); | ||
clk_disable_unprepare(info->pclk); | ||
regulator_disable(info->vref); | ||
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return 0; | ||
} | ||
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static int rockchip_saradc_resume(struct device *dev) | ||
{ | ||
struct iio_dev *indio_dev = dev_get_drvdata(dev); | ||
struct rockchip_saradc *info = iio_priv(indio_dev); | ||
int ret; | ||
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ret = regulator_enable(info->vref); | ||
if (ret) | ||
return ret; | ||
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ret = clk_prepare_enable(info->pclk); | ||
if (ret) | ||
return ret; | ||
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ret = clk_prepare_enable(info->clk); | ||
if (ret) | ||
return ret; | ||
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return ret; | ||
} | ||
#endif | ||
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static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops, | ||
rockchip_saradc_suspend, rockchip_saradc_resume); | ||
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static const struct of_device_id rockchip_saradc_match[] = { | ||
{ .compatible = "rockchip,saradc" }, | ||
{}, | ||
}; | ||
MODULE_DEVICE_TABLE(of, rockchip_saradc_match); | ||
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static struct platform_driver rockchip_saradc_driver = { | ||
.probe = rockchip_saradc_probe, | ||
.remove = rockchip_saradc_remove, | ||
.driver = { | ||
.name = "rockchip-saradc", | ||
.owner = THIS_MODULE, | ||
.of_match_table = rockchip_saradc_match, | ||
.pm = &rockchip_saradc_pm_ops, | ||
}, | ||
}; | ||
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module_platform_driver(rockchip_saradc_driver); |