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MIPS: add support for SGI Octane (IP30)
This changeset adds support for SGI Octane/Octane2 workstations. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* | ||
* IP30/Octane cpu-features overrides. | ||
* | ||
* Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | ||
* 2004-2007 Stanislaw Skowronek <skylark@unaligned.org> | ||
* 2009 Johannes Dickgreber <tanzy@gmx.de> | ||
* 2015 Joshua Kinard <kumba@gentoo.org> | ||
* | ||
*/ | ||
#ifndef __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H | ||
#define __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H | ||
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#include <asm/cpu.h> | ||
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/* | ||
* IP30 only supports R1[024]000 processors, all using the same config | ||
*/ | ||
#define cpu_has_tlb 1 | ||
#define cpu_has_tlbinv 0 | ||
#define cpu_has_segments 0 | ||
#define cpu_has_eva 0 | ||
#define cpu_has_htw 0 | ||
#define cpu_has_rixiex 0 | ||
#define cpu_has_maar 0 | ||
#define cpu_has_rw_llb 0 | ||
#define cpu_has_3kex 0 | ||
#define cpu_has_4kex 1 | ||
#define cpu_has_3k_cache 0 | ||
#define cpu_has_4k_cache 1 | ||
#define cpu_has_6k_cache 0 | ||
#define cpu_has_8k_cache 0 | ||
#define cpu_has_tx39_cache 0 | ||
#define cpu_has_fpu 1 | ||
#define cpu_has_nofpuex 0 | ||
#define cpu_has_32fpr 1 | ||
#define cpu_has_counter 1 | ||
#define cpu_has_watch 1 | ||
#define cpu_has_64bits 1 | ||
#define cpu_has_divec 0 | ||
#define cpu_has_vce 0 | ||
#define cpu_has_cache_cdex_p 0 | ||
#define cpu_has_cache_cdex_s 0 | ||
#define cpu_has_prefetch 1 | ||
#define cpu_has_mcheck 0 | ||
#define cpu_has_ejtag 0 | ||
#define cpu_has_llsc 1 | ||
#define cpu_has_mips16 0 | ||
#define cpu_has_mdmx 0 | ||
#define cpu_has_mips3d 0 | ||
#define cpu_has_smartmips 0 | ||
#define cpu_has_rixi 0 | ||
#define cpu_has_xpa 0 | ||
#define cpu_has_vtag_icache 0 | ||
#define cpu_has_dc_aliases 0 | ||
#define cpu_has_ic_fills_f_dc 0 | ||
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#define cpu_icache_snoops_remote_store 1 | ||
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#define cpu_has_mips32r1 0 | ||
#define cpu_has_mips32r2 0 | ||
#define cpu_has_mips64r1 0 | ||
#define cpu_has_mips64r2 0 | ||
#define cpu_has_mips32r6 0 | ||
#define cpu_has_mips64r6 0 | ||
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#define cpu_has_dsp 0 | ||
#define cpu_has_dsp2 0 | ||
#define cpu_has_mipsmt 0 | ||
#define cpu_has_userlocal 0 | ||
#define cpu_has_inclusive_pcaches 1 | ||
#define cpu_hwrena_impl_bits 0 | ||
#define cpu_has_perf_cntr_intr_bit 0 | ||
#define cpu_has_vz 0 | ||
#define cpu_has_fre 0 | ||
#define cpu_has_cdmm 0 | ||
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#define cpu_dcache_line_size() 32 | ||
#define cpu_icache_line_size() 64 | ||
#define cpu_scache_line_size() 128 | ||
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#endif /* __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H */ | ||
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* | ||
* HEART IRQ defines | ||
* | ||
* Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de> | ||
* 2014-2016 Joshua Kinard <kumba@gentoo.org> | ||
* | ||
*/ | ||
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#ifndef __ASM_MACH_IP30_IRQ_H | ||
#define __ASM_MACH_IP30_IRQ_H | ||
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/* | ||
* HEART has 64 hardware interrupts, but use 128 to leave room for a few | ||
* software interrupts as well (such as the CPU timer interrupt. | ||
*/ | ||
#define NR_IRQS 128 | ||
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extern void __init ip30_install_ipi(void); | ||
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/* | ||
* HEART has 64 interrupt vectors available to it, subdivided into five | ||
* priority levels. They are numbered 0 to 63. | ||
*/ | ||
#define HEART_NUM_IRQS 64 | ||
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/* | ||
* These are the five interrupt priority levels and their corresponding | ||
* CPU IPx interrupt pins. | ||
* | ||
* Level 4 - Error Interrupts. | ||
* Level 3 - HEART timer interrupt. | ||
* Level 2 - CPU IPI, CPU debug, power putton, general device interrupts. | ||
* Level 1 - General device interrupts. | ||
* Level 0 - General device GFX flow control interrupts. | ||
*/ | ||
#define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */ | ||
#define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */ | ||
#define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */ | ||
#define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */ | ||
#define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */ | ||
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/* HEART L0 Interrupts (Low Priority) */ | ||
#define HEART_L0_INT_GENERIC 0 | ||
#define HEART_L0_INT_FLOW_CTRL_HWTR_0 1 | ||
#define HEART_L0_INT_FLOW_CTRL_HWTR_1 2 | ||
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/* HEART L2 Interrupts (High Priority) */ | ||
#define HEART_L2_INT_RESCHED_CPU_0 46 | ||
#define HEART_L2_INT_RESCHED_CPU_1 47 | ||
#define HEART_L2_INT_CALL_CPU_0 48 | ||
#define HEART_L2_INT_CALL_CPU_1 49 | ||
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/* HEART L3 Interrupts (Compare/Counter Timer) */ | ||
#define HEART_L3_INT_TIMER 50 | ||
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/* HEART L4 Interrupts (Errors) */ | ||
#define HEART_L4_INT_XWID_ERR_9 51 | ||
#define HEART_L4_INT_XWID_ERR_A 52 | ||
#define HEART_L4_INT_XWID_ERR_B 53 | ||
#define HEART_L4_INT_XWID_ERR_C 54 | ||
#define HEART_L4_INT_XWID_ERR_D 55 | ||
#define HEART_L4_INT_XWID_ERR_E 56 | ||
#define HEART_L4_INT_XWID_ERR_F 57 | ||
#define HEART_L4_INT_XWID_ERR_XBOW 58 | ||
#define HEART_L4_INT_CPU_BUS_ERR_0 59 | ||
#define HEART_L4_INT_CPU_BUS_ERR_1 60 | ||
#define HEART_L4_INT_CPU_BUS_ERR_2 61 | ||
#define HEART_L4_INT_CPU_BUS_ERR_3 62 | ||
#define HEART_L4_INT_HEART_EXCP 63 | ||
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/* | ||
* Power Switch is wired via BaseIO BRIDGE slot #6. | ||
* | ||
* ACFail is wired via BaseIO BRIDGE slot #7. | ||
*/ | ||
#define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN | ||
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#include_next <irq.h> | ||
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#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2) | ||
#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3) | ||
#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4) | ||
#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5) | ||
#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6) | ||
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#endif /* __ASM_MACH_IP30_IRQ_H */ |
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
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#ifndef __ASM_MACH_IP30_KERNEL_ENTRY_H | ||
#define __ASM_MACH_IP30_KERNEL_ENTRY_H | ||
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.macro kernel_entry_setup | ||
.endm | ||
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.macro smp_slave_setup | ||
move gp, a0 | ||
.endm | ||
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#endif /* __ASM_MACH_IP30_KERNEL_ENTRY_H */ |
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* | ||
* Copyright (C) 2003, 2004 Ralf Baechle | ||
*/ | ||
#ifndef __ASM_MACH_IP30_MANGLE_PORT_H | ||
#define __ASM_MACH_IP30_MANGLE_PORT_H | ||
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#define __swizzle_addr_b(port) ((port)^3) | ||
#define __swizzle_addr_w(port) ((port)^2) | ||
#define __swizzle_addr_l(port) (port) | ||
#define __swizzle_addr_q(port) (port) | ||
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#define ioswabb(a, x) (x) | ||
#define __mem_ioswabb(a, x) (x) | ||
#define ioswabw(a, x) (x) | ||
#define __mem_ioswabw(a, x) cpu_to_le16(x) | ||
#define ioswabl(a, x) (x) | ||
#define __mem_ioswabl(a, x) cpu_to_le32(x) | ||
#define ioswabq(a, x) (x) | ||
#define __mem_ioswabq(a, x) cpu_to_le64(x) | ||
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#endif /* __ASM_MACH_IP30_MANGLE_PORT_H */ |
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* | ||
* Copyright (C) 2016 Joshua Kinard <kumba@gentoo.org> | ||
* | ||
*/ | ||
#ifndef _ASM_MACH_IP30_SPACES_H | ||
#define _ASM_MACH_IP30_SPACES_H | ||
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/* | ||
* Memory in IP30/Octane is offset 512MB in the physical address space. | ||
*/ | ||
#define PHYS_OFFSET _AC(0x20000000, UL) | ||
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#ifdef CONFIG_64BIT | ||
#define CAC_BASE _AC(0xA800000000000000, UL) | ||
#endif | ||
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#include <asm/mach-generic/spaces.h> | ||
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#endif /* _ASM_MACH_IP30_SPACES_H */ |
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* | ||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
*/ | ||
#ifndef __ASM_MIPS_MACH_IP30_WAR_H | ||
#define __ASM_MIPS_MACH_IP30_WAR_H | ||
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#define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
#define R4600_V1_HIT_CACHEOP_WAR 0 | ||
#define R4600_V2_HIT_CACHEOP_WAR 0 | ||
#define MIPS_CACHE_SYNC_WAR 0 | ||
#define BCM1250_M3_WAR 0 | ||
#define SIBYTE_1956_WAR 0 | ||
#define MIPS4K_ICACHE_REFILL_WAR 0 | ||
#define MIPS34K_MISSED_ITLB_WAR 0 | ||
#define R5432_CP0_INTERRUPT_WAR 0 | ||
#define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
#define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
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#ifdef CONFIG_CPU_R10000 | ||
#define R10000_LLSC_WAR 1 | ||
#else | ||
#define R10000_LLSC_WAR 0 | ||
#endif | ||
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#endif /* __ASM_MIPS_MACH_IP30_WAR_H */ |
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