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phy: qcom-qmp-pcie: drop power-down delay config
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[ Upstream commit e719061 ]

The power-down delay was included in the first version of the QMP driver
as an optional delay after powering on the PHY (using
POWER_DOWN_CONTROL) and just before starting it. Later changes modified
this sequence by powering on before initialising the PHY, but the
optional delay stayed where it was (i.e. before starting the PHY).

The vendor driver does not use a delay before starting the PHY and this
is likely not needed on any platform unless there is a corresponding
delay in the vendor kernel init sequence tables (i.e. in devicetree).

Let's keep the delay for now, but drop the redundant delay period
configuration while increasing the unnecessarily low timer slack
somewhat.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221012081241.18273-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Stable-dep-of: 4a9eac5 ("phy: qcom-qmp-pcie: fix sc8180x initialisation")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@jhovold @gregkh
jhovold authored and gregkh committed Dec 31, 2022
1 parent aa51fd7 commit b52920f
Showing 1 changed file with 1 addition and 26 deletions.
27 changes: 1 addition & 26 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1346,9 +1346,6 @@ struct qmp_phy_cfg {

/* true, if PHY needs delay after POWER_DOWN */
bool has_pwrdn_delay;
/* power_down delay in usec */
int pwrdn_delay_min;
int pwrdn_delay_max;

/* QMP PHY pipe clock interface rate */
unsigned long pipe_clock_rate;
Expand Down Expand Up @@ -1480,8 +1477,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.phy_status = PHYSTATUS,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
Expand All @@ -1507,8 +1502,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */

.pipe_clock_rate = 250000000,
};
Expand Down Expand Up @@ -1538,8 +1531,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
Expand Down Expand Up @@ -1568,8 +1559,6 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
.phy_status = PHYSTATUS,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
Expand All @@ -1596,8 +1585,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.phy_status = PHYSTATUS,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
Expand Down Expand Up @@ -1634,8 +1621,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.phy_status = PHYSTATUS,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
Expand Down Expand Up @@ -1672,8 +1657,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.phy_status = PHYSTATUS,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
Expand Down Expand Up @@ -1725,8 +1708,6 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
Expand Down Expand Up @@ -1755,8 +1736,6 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.phy_status = PHYSTATUS_4_20,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
Expand Down Expand Up @@ -1785,8 +1764,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.phy_status = PHYSTATUS,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
Expand Down Expand Up @@ -1815,8 +1792,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
.phy_status = PHYSTATUS_4_20,

.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
};

static void qmp_pcie_configure_lane(void __iomem *base,
Expand Down Expand Up @@ -1976,7 +1951,7 @@ static int qmp_pcie_power_on(struct phy *phy)
qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec);

if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
usleep_range(1000, 1200);

/* Pull PHY out of reset state */
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
Expand Down

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