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clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocel…
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…l_get()

[ Upstream commit 1606e81 ]

Fix clock index out of range check for module clocks in
rzg2l_cpg_clk_src_twocell_get().

Fixes: ef3c613 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210617155432.18827-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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prabhakarlad authored and gregkh committed Sep 18, 2021
1 parent 73d06a2 commit ccb34d8
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion drivers/clk/renesas/renesas-rzg2l-cpg.c
Expand Up @@ -229,7 +229,7 @@ static struct clk

case CPG_MOD:
type = "module";
if (clkidx > priv->num_mod_clks) {
if (clkidx >= priv->num_mod_clks) {
dev_err(dev, "Invalid %s clock index %u\n", type,
clkidx);
return ERR_PTR(-EINVAL);
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