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arm64: dts: qcom: sdm630: Fix TLMM node and pinctrl configuration
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[ Upstream commit 36a0d47 ]

Previous pinctrl configuration was wrong. Fix it and clean up how
multi-pin states are described.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210728222542.54269-9-konrad.dybcio@somainline.org
[bjorn: Polished the commit message]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@kholk @gregkh
kholk authored and gregkh committed Sep 18, 2021
1 parent da59af8 commit d491b7b
Showing 1 changed file with 139 additions and 73 deletions.
212 changes: 139 additions & 73 deletions arch/arm64/boot/dts/qcom/sdm630.dtsi
View file
Expand Up @@ -522,14 +522,18 @@
reg = <0x01f40000 0x20000>;
};

tlmm: pinctrl@3000000 {
tlmm: pinctrl@3100000 {
compatible = "qcom,sdm630-pinctrl";
reg = <0x03000000 0xc00000>;
reg = <0x03100000 0x400000>,
<0x03500000 0x400000>,
<0x03900000 0x400000>;
reg-names = "south", "center", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
gpio-ranges = <&tlmm 0 0 114>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <0x2>;
#interrupt-cells = <2>;

blsp1_uart1_default: blsp1-uart1-default {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
Expand All @@ -549,40 +553,48 @@
bias-disable;
};

blsp2_uart1_tx_active: blsp2-uart1-tx-active {
pins = "gpio16";
drive-strength = <2>;
bias-disable;
};

blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
pins = "gpio16";
drive-strength = <2>;
bias-pull-up;
};
blsp2_uart1_default: blsp2-uart1-active {
tx-rts {
pins = "gpio16", "gpio19";
function = "blsp_uart5";
drive-strength = <2>;
bias-disable;
};

blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
pins = "gpio17", "gpio18";
drive-strength = <2>;
bias-disable;
};
rx {
/*
* Avoid garbage data while BT module
* is powered off or not driving signal
*/
pins = "gpio17";
function = "blsp_uart5";
drive-strength = <2>;
bias-pull-up;
};

blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
pins = "gpio17", "gpio18";
drive-strength = <2>;
bias-no-pull;
cts {
/* Match the pull of the BT module */
pins = "gpio18";
function = "blsp_uart5";
drive-strength = <2>;
bias-pull-down;
};
};

blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
pins = "gpio19";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_sleep: blsp2-uart1-sleep {
tx {
pins = "gpio16";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};

blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
pins = "gpio19";
drive-strength = <2>;
bias-no-pull;
rx-cts-rts {
pins = "gpio17", "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-no-pull;
};
};

i2c1_default: i2c1-default {
Expand Down Expand Up @@ -681,50 +693,106 @@
bias-pull-up;
};

sdc1_clk_on: sdc1-clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
sdc1_state_on: sdc1-on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};

sdc1_clk_off: sdc1-clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};

sdc1_cmd_on: sdc1-cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};

sdc1_cmd_off: sdc1-cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};

sdc1_data_on: sdc1-data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
sdc1_state_off: sdc1-off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};

sdc1_data_off: sdc1-data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};

data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};

rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};

sdc1_rclk_on: sdc1-rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
sdc2_state_on: sdc2-on {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};

cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};

data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};

sd-cd {
pins = "gpio54";
bias-pull-up;
drive-strength = <2>;
};
};

sdc1_rclk_off: sdc1-rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
sdc2_state_off: sdc2-off {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};

cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};

data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};

sd-cd {
pins = "gpio54";
bias-disable;
drive-strength = <2>;
};
};
};

Expand Down Expand Up @@ -818,8 +886,8 @@
clock-names = "core", "iface", "xo", "ice";

pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;

bus-width = <8>;
non-removable;
Expand Down Expand Up @@ -964,10 +1032,8 @@
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
&blsp2_uart1_rfr_active>;
pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
&blsp2_uart1_rfr_sleep>;
pinctrl-0 = <&blsp2_uart1_default>;
pinctrl-1 = <&blsp2_uart1_sleep>;
status = "disabled";
};

Expand Down

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