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ARM: aspeed: g5: Do not set sirq polarity
commit c82bf6e upstream. A feature was added to the aspeed vuart driver to configure the vuart interrupt (sirq) polarity according to the LPC/eSPI strapping register. Systems that depend on a active low behaviour (sirq_polarity set to 0) such as OpenPower boxes also use LPC, so this relationship does not hold. Jeremy confirms that the s2600st which is strapped for eSPI also does not have this relationship. The property was added for a Tyan S7106 system which is not supported in the kernel tree. Should this or other systems wish to use this feature of the driver they should add it to the machine specific device tree. Fixes: c791fc7 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...") Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Jeremy Kerr <jk@ozlabs.org> Reviewed-by: Jeremy Kerr <jk@ozlabs.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200812112400.2406734-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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