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clk: renesas: r9a06g032: Fix UART clkgrp bitsel
[ Upstream commit 2dee50a ] There are two UART clock groups, each having a mux to select its upstream clock source. The register/bit definitions for accessing these two muxes appear to have been reversed since introduction. Correct them so as to match the hardware manual. Fixes: 4c3d885 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
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