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remoteproc/mediatek: Add support for mt8192 SCP
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Add support for mt8192 SCP.

Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20200921094847.2112399-1-pihsun@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@peter50216 @andersson
peter50216 authored and andersson committed Sep 26, 2020
1 parent 1894622 commit fd0b6c1
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Showing 3 changed files with 204 additions and 36 deletions.
32 changes: 32 additions & 0 deletions drivers/remoteproc/mtk_common.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,23 @@
#define MT8183_SCP_CACHESIZE_8KB BIT(8)
#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)

#define MT8192_L2TCM_SRAM_PD_0 0x210C0
#define MT8192_L2TCM_SRAM_PD_1 0x210C4
#define MT8192_L2TCM_SRAM_PD_2 0x210C8
#define MT8192_L1TCM_SRAM_PDN 0x2102C
#define MT8192_CPU0_SRAM_PD 0x21080

#define MT8192_SCP2APMCU_IPC_SET 0x24080
#define MT8192_SCP2APMCU_IPC_CLR 0x24084
#define MT8192_SCP_IPC_INT_BIT BIT(0)
#define MT8192_SCP2SPM_IPC_CLR 0x24094
#define MT8192_GIPC_IN_SET 0x24098
#define MT8192_HOST_IPC_INT_BIT BIT(0)

#define MT8192_CORE0_SW_RSTN_CLR 0x30000
#define MT8192_CORE0_SW_RSTN_SET 0x30004
#define MT8192_CORE0_WDT_CFG 0x30034

#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288

Expand All @@ -50,6 +67,19 @@ struct scp_ipi_desc {
void *priv;
};

struct mtk_scp;

struct mtk_scp_of_data {
int (*scp_before_load)(struct mtk_scp *scp);
void (*scp_irq_handler)(struct mtk_scp *scp);
void (*scp_reset_assert)(struct mtk_scp *scp);
void (*scp_reset_deassert)(struct mtk_scp *scp);
void (*scp_stop)(struct mtk_scp *scp);

u32 host_to_scp_reg;
u32 host_to_scp_int_bit;
};

struct mtk_scp {
struct device *dev;
struct rproc *rproc;
Expand All @@ -58,6 +88,8 @@ struct mtk_scp {
void __iomem *sram_base;
size_t sram_size;

const struct mtk_scp_of_data *data;

struct mtk_share_obj __iomem *recv_buf;
struct mtk_share_obj __iomem *send_buf;
struct scp_run run;
Expand Down
203 changes: 169 additions & 34 deletions drivers/remoteproc/mtk_scp.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -124,9 +124,6 @@ static int scp_ipi_init(struct mtk_scp *scp)
size_t send_offset = SCP_FW_END - sizeof(struct mtk_share_obj);
size_t recv_offset = send_offset - sizeof(struct mtk_share_obj);

/* Disable SCP to host interrupt */
writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);

/* shared buffer initialization */
scp->recv_buf =
(struct mtk_share_obj __iomem *)(scp->sram_base + recv_offset);
Expand All @@ -138,7 +135,7 @@ static int scp_ipi_init(struct mtk_scp *scp)
return 0;
}

static void scp_reset_assert(const struct mtk_scp *scp)
static void mt8183_scp_reset_assert(struct mtk_scp *scp)
{
u32 val;

Expand All @@ -147,7 +144,7 @@ static void scp_reset_assert(const struct mtk_scp *scp)
writel(val, scp->reg_base + MT8183_SW_RSTN);
}

static void scp_reset_deassert(const struct mtk_scp *scp)
static void mt8183_scp_reset_deassert(struct mtk_scp *scp)
{
u32 val;

Expand All @@ -156,17 +153,19 @@ static void scp_reset_deassert(const struct mtk_scp *scp)
writel(val, scp->reg_base + MT8183_SW_RSTN);
}

static irqreturn_t scp_irq_handler(int irq, void *priv)
static void mt8192_scp_reset_assert(struct mtk_scp *scp)
{
struct mtk_scp *scp = priv;
u32 scp_to_host;
int ret;
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
}

ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(scp->dev, "failed to enable clocks\n");
return IRQ_NONE;
}
static void mt8192_scp_reset_deassert(struct mtk_scp *scp)
{
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR);
}

static void mt8183_scp_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;

scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST);
if (scp_to_host & MT8183_SCP_IPC_INT_BIT)
Expand All @@ -177,6 +176,40 @@ static irqreturn_t scp_irq_handler(int irq, void *priv)
/* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */
writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT,
scp->reg_base + MT8183_SCP_TO_HOST);
}

static void mt8192_scp_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;

scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);

if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
scp_ipi_handler(scp);
else
scp_wdt_handler(scp, scp_to_host);

/*
* SCP won't send another interrupt until we clear
* MT8192_SCP2APMCU_IPC.
*/
writel(MT8192_SCP_IPC_INT_BIT,
scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
}

static irqreturn_t scp_irq_handler(int irq, void *priv)
{
struct mtk_scp *scp = priv;
int ret;

ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(scp->dev, "failed to enable clocks\n");
return IRQ_NONE;
}

scp->data->scp_irq_handler(scp);

clk_disable_unprepare(scp->clk);

return IRQ_HANDLED;
Expand Down Expand Up @@ -238,20 +271,10 @@ static int scp_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
return ret;
}

static int scp_load(struct rproc *rproc, const struct firmware *fw)
static int mt8183_scp_before_load(struct mtk_scp *scp)
{
const struct mtk_scp *scp = rproc->priv;
struct device *dev = scp->dev;
int ret;

ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(dev, "failed to enable clocks\n");
return ret;
}

/* Hold SCP in reset while loading FW. */
scp_reset_assert(scp);
/* Clear SCP to host interrupt */
writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);

/* Reset clocks before loading FW */
writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
Expand All @@ -272,6 +295,67 @@ static int scp_load(struct rproc *rproc, const struct firmware *fw)
scp->reg_base + MT8183_SCP_CACHE_CON);
writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);

return 0;
}

static void mt8192_power_on_sram(void *addr)
{
int i;

for (i = 31; i >= 0; i--)
writel(GENMASK(i, 0), addr);
writel(0, addr);
}

static void mt8192_power_off_sram(void *addr)
{
int i;

writel(0, addr);
for (i = 0; i < 32; i++)
writel(GENMASK(i, 0), addr);
}

static int mt8192_scp_before_load(struct mtk_scp *scp)
{
/* clear SPM interrupt, SCP2SPM_IPC_CLR */
writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);

writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);

dsb(sy);

readl(scp->reg_base + MT8192_CORE0_SW_RSTN_SET);

/* enable SRAM clock */
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);

return 0;
}

static int scp_load(struct rproc *rproc, const struct firmware *fw)
{
struct mtk_scp *scp = rproc->priv;
struct device *dev = scp->dev;
int ret;

ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(dev, "failed to enable clocks\n");
return ret;
}

/* Hold SCP in reset while loading FW. */
scp->data->scp_reset_assert(scp);

ret = scp->data->scp_before_load(scp);
if (ret < 0)
return ret;

ret = scp_elf_load_segments(rproc, fw);
clk_disable_unprepare(scp->clk);

Expand All @@ -293,7 +377,7 @@ static int scp_start(struct rproc *rproc)

run->signaled = false;

scp_reset_deassert(scp);
scp->data->scp_reset_deassert(scp);

ret = wait_event_interruptible_timeout(
run->wq,
Expand All @@ -309,13 +393,14 @@ static int scp_start(struct rproc *rproc)
dev_err(dev, "wait SCP interrupted by a signal!\n");
goto stop;
}

clk_disable_unprepare(scp->clk);
dev_info(dev, "SCP is ready. FW version %s\n", run->fw_ver);

return 0;

stop:
scp_reset_assert(scp);
scp->data->scp_reset_assert(scp);
clk_disable_unprepare(scp->clk);
return ret;
}
Expand All @@ -329,7 +414,7 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
offset = da;
if (offset >= 0 && (offset + len) < scp->sram_size)
return (void __force *)scp->sram_base + offset;
} else {
} else if (scp->dram_size) {
offset = da - scp->dma_addr;
if (offset >= 0 && (offset + len) < scp->dram_size)
return (void __force *)scp->cpu_addr + offset;
Expand All @@ -338,6 +423,25 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
return NULL;
}

static void mt8183_scp_stop(struct mtk_scp *scp)
{
/* Disable SCP watchdog */
writel(0, scp->reg_base + MT8183_WDT_CFG);
}

static void mt8192_scp_stop(struct mtk_scp *scp)
{
/* Disable SRAM clock */
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
mt8192_power_off_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
mt8192_power_off_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);

/* Disable SCP watchdog */
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
}

static int scp_stop(struct rproc *rproc)
{
struct mtk_scp *scp = (struct mtk_scp *)rproc->priv;
Expand All @@ -349,9 +453,8 @@ static int scp_stop(struct rproc *rproc)
return ret;
}

scp_reset_assert(scp);
/* Disable SCP watchdog */
writel(0, scp->reg_base + MT8183_WDT_CFG);
scp->data->scp_reset_assert(scp);
scp->data->scp_stop(scp);
clk_disable_unprepare(scp->clk);

return 0;
Expand Down Expand Up @@ -443,6 +546,13 @@ static int scp_map_memory_region(struct mtk_scp *scp)
int ret;

ret = of_reserved_mem_device_init(scp->dev);

/* reserved memory is optional. */
if (ret == -ENODEV) {
dev_info(scp->dev, "skipping reserved memory initialization.");
return 0;
}

if (ret) {
dev_err(scp->dev, "failed to assign memory-region: %d\n", ret);
return -ENOMEM;
Expand All @@ -460,6 +570,9 @@ static int scp_map_memory_region(struct mtk_scp *scp)

static void scp_unmap_memory_region(struct mtk_scp *scp)
{
if (scp->dram_size == 0)
return;

dma_free_coherent(scp->dev, scp->dram_size, scp->cpu_addr,
scp->dma_addr);
of_reserved_mem_device_release(scp->dev);
Expand Down Expand Up @@ -536,6 +649,7 @@ static int scp_probe(struct platform_device *pdev)
scp = (struct mtk_scp *)rproc->priv;
scp->rproc = rproc;
scp->dev = dev;
scp->data = of_device_get_match_data(dev);
platform_set_drvdata(pdev, scp);

res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
Expand Down Expand Up @@ -642,8 +756,29 @@ static int scp_remove(struct platform_device *pdev)
return 0;
}

static const struct mtk_scp_of_data mt8183_of_data = {
.scp_before_load = mt8183_scp_before_load,
.scp_irq_handler = mt8183_scp_irq_handler,
.scp_reset_assert = mt8183_scp_reset_assert,
.scp_reset_deassert = mt8183_scp_reset_deassert,
.scp_stop = mt8183_scp_stop,
.host_to_scp_reg = MT8183_HOST_TO_SCP,
.host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT,
};

static const struct mtk_scp_of_data mt8192_of_data = {
.scp_before_load = mt8192_scp_before_load,
.scp_irq_handler = mt8192_scp_irq_handler,
.scp_reset_assert = mt8192_scp_reset_assert,
.scp_reset_deassert = mt8192_scp_reset_deassert,
.scp_stop = mt8192_scp_stop,
.host_to_scp_reg = MT8192_GIPC_IN_SET,
.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
};

static const struct of_device_id mtk_scp_of_match[] = {
{ .compatible = "mediatek,mt8183-scp"},
{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data },
{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
{},
};
MODULE_DEVICE_TABLE(of, mtk_scp_of_match);
Expand Down
5 changes: 3 additions & 2 deletions drivers/remoteproc/mtk_scp_ipi.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
ret = -ETIMEDOUT;
goto clock_disable;
}
} while (readl(scp->reg_base + MT8183_HOST_TO_SCP));
} while (readl(scp->reg_base + scp->data->host_to_scp_reg));

scp_memcpy_aligned(send_obj->share_buf, buf, len);

Expand All @@ -189,7 +189,8 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,

scp->ipi_id_ack[id] = false;
/* send the command to SCP */
writel(MT8183_HOST_IPC_INT_BIT, scp->reg_base + MT8183_HOST_TO_SCP);
writel(scp->data->host_to_scp_int_bit,
scp->reg_base + scp->data->host_to_scp_reg);

if (wait) {
/* wait for SCP's ACK */
Expand Down

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