fixes as per bug 14659 and others

doc/api.rst

@@ -41,7 +41,7 @@ to ``sdram_conf.h``.
   This defines the minimum time between refreshes in SDRAM Clk cycles. Must be in the range from 2 to 4 inclusive.
 
 **SDRAM_EXTERNAL_MEMORY_ACCESSOR**
-  This defines if the memory is accessed by another device(other than the XCore). If not defined then faster code will be produced.
+  This defines if the memory is accessed by another device(other than the xCORE). If not defined then faster code will be produced.
 
 **SDRAM_CLOCK_DIVIDER**
   Set ``SDRAM_CLOCK_DIVIDER`` to divide down the reference clock to get the desired SDRAM Clock. The reference clock is divided by 2*SDRAM_CLOCK_DIVIDER.
@@ -102,11 +102,11 @@ These are the functions that are called from the application and are included in
 Server Functions
 ++++++++++++++++
 
-C and XC Interface
+C and xC Interface
 ------------------
 .. doxygenfunction:: sdram_server
 
-XC Interface
+xC Interface
 ------------
 .. doxygenfunction:: sdram_wait_until_idle
 .. doxygenfunction:: sdram_buffer_write
@@ -122,7 +122,7 @@ C Interface
 .. doxygenfunction:: sdram_buffer_read_p
 .. doxygenfunction:: sdram_full_row_read_p
 
-C and XC Interface
+C and xC Interface
 ------------------
 .. doxygenfunction:: sdram_col_write
 .. doxygenfunction:: sdram_shutdown
@@ -134,7 +134,7 @@ These are the functions that are called from the application and are included in
 
 Server Functions
 ++++++++++++++++
-XC Interface
+xC Interface
 ------------
 .. doxygenfunction:: mm_read_words
 .. doxygenfunction:: mm_write_words

doc/examples.rst

@@ -12,8 +12,8 @@ This application demonstrates how the module is used to accesses memory on the S
 Getting Started
 +++++++++++++++
 
-   #. Plug the XA-SK-SDRAM Slice Card into the 'STAR' slot of the Slicekit Core Board.
-   #. Plug the XA-SK-XTAG2 Card into the Slicekit Core Board.
+   #. Plug the XA-SK-SDRAM Slice Card into the 'STAR' slot of the sliceKIT Core Board.
+   #. Plug the XA-SK-XTAG2 Card into the sliceKIT Core Board.
    #. Ensure the XMOS LINK switch on the XA-SK-XTAG2 is set to "off".
    #. Open ``app_sdram_demo.xc`` and build it.
    #. run the program on the hardware.
@@ -36,13 +36,13 @@ Notes
 app_sdram_regress
 -----------------
 
-This application serves as a software regression to aid implementing new SDRAM interfaces and verifying current ones. The demo runs a series of regression tests of increasing difficulty, beginning from using a single core for the sdram_server with one core loaded progressing to all cores being loaded to simulate an XCore under full load. 
+This application serves as a software regression to aid implementing new SDRAM interfaces and verifying current ones. The demo runs a series of regression tests of increasing difficulty, beginning from using a single core for the sdram_server with one core loaded progressing to all cores being loaded to simulate an xCORE under full load. 
 
 Getting Started
 +++++++++++++++
 
-   #. Plug the XA-SK-SDRAM Slice Card into the 'STAR' slot of the Slicekit Core Board.
-   #. Plug the XA-SK-XTAG2 Card into the Slicekit Core Board.
+   #. Plug the XA-SK-SDRAM Slice Card into the 'STAR' slot of the sliceKIT Core Board.
+   #. Plug the XA-SK-XTAG2 Card into the sliceKIT Core Board.
    #. Ensure the XMOS LINK switch on the XA-SK-XTAG2 is set to "off".
    #. Open ``app_sdram_regress.xc`` and build it.
    #. run the program on the hardware.
@@ -62,8 +62,8 @@ This application benchmarks the performance of the module. It does no correctnes
 Getting Started
 +++++++++++++++
 
-   #. Plug the XA-SK-SDRAM Slice Card into the 'STAR' slot of the Slicekit Core Board.
-   #. Plug the XA-SK-XTAG2 Card into the Slicekit Core Board.
+   #. Plug the XA-SK-SDRAM Slice Card into the 'STAR' slot of the sliceKIT Core Board.
+   #. Plug the XA-SK-XTAG2 Card into the sliceKIT Core Board.
    #. Ensure the XMOS LINK switch on the XA-SK-XTAG2 is set to "off".
    #. Open ``app_sdram_benchmark.xc`` and build it.
    #. run the program on the hardware.

doc/hw.rst

@@ -12,15 +12,15 @@ Slicekit
 
 This module may be evaluated using the Slicekit Modular Development Platform, available from digikey. Required board SKUs are:
 
-   * XP-SKC-L2 (Slicekit L2 Core Board) plus XA-SK-SDRAM plus XA-SK-XTAG2 (Slicekit XTAG adaptor) 
+   * XP-SKC-L2 (Slicekit L16 Core Board) plus XA-SK-SDRAM plus XA-SK-XTAG2 (Slicekit XTAG adaptor) 
 
 Demonstration Applications
 --------------------------
 
 Testbench Application
 +++++++++++++++++++++
 
-This application serves as a software regression to aid implementing new SDRAM interfaces and verifying current ones. The demo runs a series of regression tests of increasing difficulty, beginning from using a single core for the server and a single core for the sdram_server progressing to all cores being loaded to simulate an XCore under full load. 
+This application serves as a software regression to aid implementing new SDRAM interfaces and verifying current ones. The demo runs a series of regression tests of increasing difficulty, beginning from using a single core for the server and a single core for the sdram_server progressing to all cores being loaded to simulate an xCORE under full load. 
 
    * Package: sc_sdram_burst
    * Application: app_sdram_regress
@@ -37,20 +37,19 @@ This application benchmarks the performance of the module. It does no correctnes
 Demo Application
 ++++++++++++++++
 
-This application demonstrates how the module is used to accesses memory on the SDRAM.
+This application demonstrates how the module is used to access memory on the SDRAM.
 
    * Package: sc_sdram_burst
    * Application: app_sdram_demo
 
 Display Controller Application
 ++++++++++++++++++++++++++++++
 
-This combination demo employs this module along with the module_lcd LCD driver and the module_framebuffer framebuffer framework component to implement a 480x272 display controller.
+This combination demo employs this module along with the ``module_lcd`` LCD driver and the ``module_display_controller'' framebuffer framework component to implement a 480x272 display controller.
 
 Required board SKUs for this demo are:
 
-   * XP-SKC-L2 (Slicekit L2 Core Board) plus XA-SK-SDRAM plus XA-SK-LCD480 plus XA-SK-XTAG2 (Slicekit XTAG adaptor) 
-
+   * XP-SKC-L2 (sliceKIT L16 Core Board) plus XA-SK-SDRAM plus XA-SK-LCD480 plus XA-SK-XTAG2 (sliceKIT XTAG adaptor) 
    * Package: sw_display_controller
    * Application: app_graphics_demo
 

doc/overview.rst

@@ -4,9 +4,9 @@ Overview
 SDRAM Controller Component
 --------------------------
 
-The SDRAM module is designed for 16 bit read and write access of arbitrary length at up to 50MHz clock rates. It uses an optimised pinout with address and data lines overlaid along with other pinout optimisations in order to implement 16 bit read/write with up to 13 address lines in just 20 pins.
+The SDRAM module is designed for 16 bit read and write access of arbitrary length at up to 50MHz clock rates. It uses an optimal pinout with address and data lines overlaid to implement 16 bit read/write with up to 13 address lines in just 20 pins.
 
-The module currently targets the ISSI 6400 SDRAM but is easily specialised for the smaller and larger members of this family as well as single data rate SDRAM memory from other manufacturers.
+The module currently targets the ISSI 6400 SDRAM but may easily any single data rate SDRAM memory from other manufacturers.
 
 SDRAM Component Features
 ++++++++++++++++++++++++
@@ -30,7 +30,7 @@ The SDRAM component has the following features:
 
 
 
-Memory requirements
+Memory Requirements
 +++++++++++++++++++
 
 +------------------+----------------------------------------+
@@ -59,10 +59,10 @@ Resource requirements
 Performance
 +++++++++++
 
-The achievable effective bandwidth varies according to the available XCore MIPS. This information has been obtained by testing on real hardware.
+The achievable effective bandwidth varies according to the available xCORE MIPS. This information has been obtained by testing on real hardware.
 
 +------------+-------+--------------+----------------+------------------+
-| XCore MIPS | Cores | System Clock |Max Read (MB/s) | Max Write (MB/s) | 
+| xCORE MIPS | Cores | System Clock |Max Read (MB/s) | Max Write (MB/s) | 
 +============+=======+==============+================+==================+
 | 50         | 8     | 400MHz       | 66.84          | 70.75            | 
 +------------+-------+--------------+----------------+------------------+
@@ -98,7 +98,7 @@ SDRAM Memory Mapper
 
 A memory mapper module called ``module_sdram_memory_mapper`` may be used in order to abstract the physical geometry of the SDRAM from the application. Its only function is to map the physical geometry of the SDRAM to a virtual byte addresses that the application can use. 
 
-Memory requirements
+Memory Requirements
 +++++++++++++++++++
 
 +------------------+----------------------------------------+
@@ -109,7 +109,7 @@ Memory requirements
 | Program          | 32 bytes                               |
 +------------------+----------------------------------------+
 
-Resource requirements
+Resource Requirements
 +++++++++++++++++++++
 
 +---------------+-------+

doc/programming.rst

@@ -88,7 +88,7 @@ Notes
 The ``sdram_server`` and application must be on the same tile.
 
 
-Source code structure
+Source Code Structure
 ---------------------
 
 Directory Structure
@@ -120,7 +120,7 @@ module. The API is described in :ref:`sec_api`.
 Module Usage
 ------------
 
-To use the SDRAM module first set up the directory structure as shown above. Create a file in the ``app`` folder called ``sdram_conf.h`` and into it insert a define for ``SDRAM_DEFAULT_IMPLEMENTATION``.  It should be defined as the implementation you want to use, for example for the Slicekit the following would be correct::
+To use the SDRAM module first set up the directory structure as shown above. Create a file in the ``app`` folder called ``sdram_conf.h`` and into it insert a define for ``SDRAM_DEFAULT_IMPLEMENTATION``.  It should be defined as the implementation you want to use, for example for the sliceKIT the following would be correct::
 
 	#define SDRAM_DEFAULT_IMPLEMENTATION PINOUT_V1_IS42S16160D
 
@@ -151,7 +151,7 @@ Now the ``application`` function is able to use the SDRAM server.
 SDRAM Memory Mapper Programming Guide
 =====================================
 
-The SDRAM memory mapper has a simple interface where to the ``mm_read_words`` and ``mm_write_words`` a virtual address is passes, this virtual address is mapped to a physical address and the I/O is performed there. The ``mm_wait_until_idle`` exists so that the application can run the I/O commands in a non-blocking manner then confirm that the command has when the ``mm_wait_until_idle`` returns.
+The SDRAM memory mapper has a simple interface where to the ``mm_read_words`` and ``mm_write_words`` functions a virtual address is passed, this virtual address is mapped to a physical address and the I/O is performed there. The ``mm_wait_until_idle`` exists so that the application can run the I/O commands in a non-blocking manner then confirm that the command has when the ``mm_wait_until_idle`` returns.
 
 
 Software Requirements

module_sdram/src/sdram.h

@@ -89,7 +89,7 @@ void sdram_buffer_write(chanend c_server, unsigned bank, unsigned start_row,
 void sdram_buffer_write_p(chanend c_server, unsigned bank, unsigned start_row,
     unsigned start_col, unsigned width_words, intptr_t buffer);
 
-/** \brief Used read a full row of data from a buffer to the SDRAM
+/** \brief Used to read a full row of data from a buffer to the SDRAM
  *
  * \param server The channel end connecting the application to the server.
  * \param bank The bank number in the SDRAM from which the SDRAM data should be read.
@@ -102,7 +102,7 @@ void sdram_buffer_write_p(chanend c_server, unsigned bank, unsigned start_row,
 void sdram_full_row_read(chanend c_server, unsigned bank, unsigned row,
     unsigned buffer[]);
 
-/** \brief Used read a full row of data from a buffer to the SDRAM
+/** \brief Used to read a full row of data from a buffer to the SDRAM
  *
  * \param server The channel end connecting the application to the server.
  * \param bank The bank number in the SDRAM from which the SDRAM data should be read.
@@ -115,7 +115,7 @@ void sdram_full_row_read(chanend c_server, unsigned bank, unsigned row,
 void sdram_full_row_read_p(chanend c_server, unsigned bank, unsigned row,
     intptr_t buffer);
 
-/** \brief Used write a full row of data from a buffer to the SDRAM
+/** \brief Used to write a full row of data from a buffer to the SDRAM
  *
  * \param server The channel end connecting the application to the server
  * \param bank The bank number in the SDRAM into which the buffer of data should be written
@@ -128,7 +128,7 @@ void sdram_full_row_read_p(chanend c_server, unsigned bank, unsigned row,
 void sdram_full_row_write(chanend c_server, unsigned bank, unsigned row,
     unsigned buffer[]);
 
-/** \brief Used write a full row of data from a buffer to the SDRAM
+/** \brief Used to write a full row of data from a buffer to the SDRAM
  *
  * \param server The channel end connecting the application to the server
  * \param bank The bank number in the SDRAM into which the buffer of data should be written
@@ -141,7 +141,7 @@ void sdram_full_row_write(chanend c_server, unsigned bank, unsigned row,
 void sdram_full_row_write_p(chanend c_server, unsigned bank, unsigned row,
     intptr_t buffer);
 
-/** \brief Used write a single column of data to the SDRAM
+/** \brief Used to write a single column of data to the SDRAM
  *
  * \param server The channel end connecting the application to the server
  * \param bank The bank number in the SDRAM into which the data should be written