dialects: (riscv) remove Register class

tests/dialects/test_riscv.py

@@ -15,12 +15,12 @@ def test_add_op():
 
     assert a1.type is add_op.rs1.type
     assert a2.type is add_op.rs2.type
-    assert isinstance(a0.type, riscv.RegisterType)
-    assert isinstance(a1.type, riscv.RegisterType)
-    assert isinstance(a2.type, riscv.RegisterType)
-    assert a0.type.data.name == "a0"
-    assert a1.type.data.name == "a1"
-    assert a2.type.data.name == "a2"
+    assert isinstance(a0.type, riscv.IntRegisterType)
+    assert isinstance(a1.type, riscv.IntRegisterType)
+    assert isinstance(a2.type, riscv.IntRegisterType)
+    assert a0.type.data == "a0"
+    assert a1.type.data == "a1"
+    assert a2.type.data == "a2"
 
 
 def test_csr_op():
@@ -234,9 +234,9 @@ def test_immediate_shift_inst():
 
 def test_float_register():
     with pytest.raises(VerifyException, match="not in"):
-        riscv.RegisterType(riscv.Register("ft9"))
+        riscv.IntRegisterType("ft9")
     with pytest.raises(VerifyException, match="not in"):
-        riscv.FloatRegisterType(riscv.Register("a0"))
+        riscv.FloatRegisterType("a0")
 
     a1 = TestSSAValue(riscv.Registers.A1)
     a2 = TestSSAValue(riscv.Registers.A2)

tests/interpreters/test_riscv_func_interpreter.py

@@ -13,7 +13,7 @@
 @ModuleOp
 @Builder.implicit_region
 def my_module():
-    @Builder.implicit_region((riscv.RegisterType(riscv.Register()),))
+    @Builder.implicit_region((riscv.IntRegisterType.unallocated(),))
     def body(args: tuple[BlockArgument, ...]) -> None:
         riscv_func.ReturnOp(args)
 

xdsl/backend/riscv/lowering/riscv_arith_lowering.py

@@ -47,7 +47,7 @@ def match_and_rewrite(self, op: arith.Constant, rewriter: PatternRewriter) -> No
             if isinstance(op.result.type, Float32Type):
                 lui = riscv.LiOp(
                     convert_float_to_int(op.value.value.data),
-                    rd=riscv.RegisterType(riscv.Register()),
+                    rd=riscv.IntRegisterType.unallocated(),
                 )
                 fld = riscv.FCvtSWOp(lui.rd)
                 rewriter.replace_op(op, [lui, fld])

xdsl/backend/riscv/register_allocation.py

@@ -1,7 +1,7 @@
 from abc import ABC
 
 from xdsl.dialects.builtin import ModuleOp
-from xdsl.dialects.riscv import FloatRegisterType, Register, RegisterType, RISCVOp
+from xdsl.dialects.riscv import FloatRegisterType, IntRegisterType, RISCVOp
 from xdsl.ir import SSAValue
 
 
@@ -53,7 +53,7 @@ class RegisterAllocatorLivenessBlockNaive(RegisterAllocator):
 
     def __init__(self, limit_registers: int = 0) -> None:
         self.idx = 0
-        self._register_types = (RegisterType, FloatRegisterType)
+        self._register_types = (IntRegisterType, FloatRegisterType)
 
         """
         Assume that all the registers are available except the ones explicitly reserved
@@ -62,12 +62,12 @@ def __init__(self, limit_registers: int = 0) -> None:
         self.reserved_registers = {"zero", "sp", "gp", "tp", "fp", "s0"}
 
         self.register_sets = {
-            RegisterType: [
+            IntRegisterType: [
                 reg
-                for reg in Register.RV32I_INDEX_BY_NAME
+                for reg in IntRegisterType.RV32I_INDEX_BY_NAME
                 if reg not in self.reserved_registers
             ],
-            FloatRegisterType: list(Register.RV32F_INDEX_BY_NAME.keys()),
+            FloatRegisterType: list(FloatRegisterType.RV32F_INDEX_BY_NAME.keys()),
         }
 
         for reg_type, reg_set in self.register_sets.items():
@@ -81,10 +81,10 @@ def _allocate(self, reg: SSAValue) -> bool:
             available_regs = self.register_sets.get(reg_type, [])
 
             if not available_regs:
-                reg.type = reg_type(Register(f"j{self.idx}"))
+                reg.type = reg_type(f"j{self.idx}")
                 self.idx += 1
             else:
-                reg.type = reg_type(Register(available_regs.pop()))
+                reg.type = reg_type(available_regs.pop())
 
             return True
 
@@ -132,7 +132,7 @@ class RegisterAllocatorBlockNaive(RegisterAllocator):
 
     def __init__(self, limit_registers: int = 0) -> None:
         self.idx = 0
-        self._register_types = (RegisterType, FloatRegisterType)
+        self._register_types = (IntRegisterType, FloatRegisterType)
         _ = limit_registers
 
         """
@@ -142,12 +142,12 @@ def __init__(self, limit_registers: int = 0) -> None:
         reserved_registers = {"zero", "sp", "gp", "tp", "fp", "s0"}
 
         self.register_sets = {
-            RegisterType: [
+            IntRegisterType: [
                 reg
-                for reg in Register.RV32I_INDEX_BY_NAME
+                for reg in IntRegisterType.RV32I_INDEX_BY_NAME
                 if reg not in reserved_registers
             ],
-            FloatRegisterType: list(Register.RV32F_INDEX_BY_NAME.keys()),
+            FloatRegisterType: list(FloatRegisterType.RV32F_INDEX_BY_NAME.keys()),
         }
 
     def allocate_registers(self, module: ModuleOp) -> None:
@@ -173,20 +173,18 @@ def allocate_registers(self, module: ModuleOp) -> None:
 
                                 # If we run out of real registers, allocate a j register
                                 if not available_regs:
-                                    result.type = reg_type(Register(f"j{self.idx}"))
+                                    result.type = reg_type(f"j{self.idx}")
                                     self.idx += 1
                                 else:
-                                    result.type = reg_type(
-                                        Register(available_regs.pop())
-                                    )
+                                    result.type = reg_type(available_regs.pop())
 
 
 class RegisterAllocatorJRegs(RegisterAllocator):
     idx: int
 
     def __init__(self, limit_registers: int = 0) -> None:
         self.idx = 0
-        self._register_types = (RegisterType, FloatRegisterType)
+        self._register_types = (IntRegisterType, FloatRegisterType)
         _ = limit_registers
 
     def allocate_registers(self, module: ModuleOp) -> None:
@@ -202,5 +200,5 @@ def allocate_registers(self, module: ModuleOp) -> None:
                 if isinstance(result.type, self._register_types):
                     if not result.type.is_allocated:
                         reg_type = type(result.type)
-                        result.type = reg_type(Register(f"j{self.idx}"))
+                        result.type = reg_type(f"j{self.idx}")
                         self.idx += 1