Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

dialect: (builtin) Custom syntax for UnrealizedConversionCastOp #1406

Merged
merged 9 commits into from
Aug 4, 2023
Merged

dialect: (builtin) Custom syntax for UnrealizedConversionCastOp #1406

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
9 commits
Select commit Hold shift + click to select a range
cfc6db9
dialect: (builtin) Custom syntax for UnrealizedConversionCastOp
kingiler Aug 3, 2023
4ad1145
dialect: (builtin) add test for unrealized_conversion_cast
kingiler Aug 3, 2023
d957a4f
misc: better coding style
kingiler Aug 3, 2023
e1e8dd0
dialect: (builtin) add print and parsing of attr dict for UnrealizedC…
kingiler Aug 4, 2023
eeea90c
Merge branch 'main' into custom_syntax_cast
kingiler Aug 4, 2023
0c5256c
misc: update test
kingiler Aug 4, 2023
46f0fb5
Merge branch 'main' into custom_syntax_cast
kingiler Aug 4, 2023
db604eb
tests: Add interop for UnrealizedConversionCastOp
kingiler Aug 4, 2023
c86f44c
Merge branch 'main' into custom_syntax_cast
kingiler Aug 4, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 8 additions & 8 deletions tests/filecheck/backend/rvscf_scf_lowering.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,18 +17,18 @@ builtin.module {
// CHECK-NEXT: %1 = arith.constant 10 : index
// CHECK-NEXT: %2 = arith.constant 1 : index
// CHECK-NEXT: %3 = arith.constant 0 : index
// CHECK-NEXT: %4 = "builtin.unrealized_conversion_cast"(%0) : (index) -> !riscv.reg<>
// CHECK-NEXT: %5 = "builtin.unrealized_conversion_cast"(%1) : (index) -> !riscv.reg<>
// CHECK-NEXT: %6 = "builtin.unrealized_conversion_cast"(%2) : (index) -> !riscv.reg<>
// CHECK-NEXT: %7 = "builtin.unrealized_conversion_cast"(%3) : (index) -> !riscv.reg<>
// CHECK-NEXT: %4 = builtin.unrealized_conversion_cast %0 : index to !riscv.reg<>
// CHECK-NEXT: %5 = builtin.unrealized_conversion_cast %1 : index to !riscv.reg<>
// CHECK-NEXT: %6 = builtin.unrealized_conversion_cast %2 : index to !riscv.reg<>
// CHECK-NEXT: %7 = builtin.unrealized_conversion_cast %3 : index to !riscv.reg<>
// CHECK-NEXT: %8 = "riscv_scf.for"(%4, %5, %6, %7) ({
// CHECK-NEXT: ^0(%9 : !riscv.reg<>, %10 : !riscv.reg<>):
// CHECK-NEXT: %11 = "builtin.unrealized_conversion_cast"(%10) : (!riscv.reg<>) -> index
// CHECK-NEXT: %12 = "builtin.unrealized_conversion_cast"(%9) : (!riscv.reg<>) -> index
// CHECK-NEXT: %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg<> to index
// CHECK-NEXT: %12 = builtin.unrealized_conversion_cast %9 : !riscv.reg<> to index
// CHECK-NEXT: %13 = arith.addi %12, %11 : index
// CHECK-NEXT: %14 = "builtin.unrealized_conversion_cast"(%13) : (index) -> !riscv.reg<>
// CHECK-NEXT: %14 = builtin.unrealized_conversion_cast %13 : index to !riscv.reg<>
// CHECK-NEXT: "riscv_scf.yield"(%14) : (!riscv.reg<>) -> ()
// CHECK-NEXT: }) : (!riscv.reg<>, !riscv.reg<>, !riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
// CHECK-NEXT: %15 = "builtin.unrealized_conversion_cast"(%8) : (!riscv.reg<>) -> index
// CHECK-NEXT: %15 = builtin.unrealized_conversion_cast %8 : !riscv.reg<> to index
// CHECK-NEXT: }

16 changes: 11 additions & 5 deletions tests/filecheck/dialects/builtin/unrealized_conv_cast.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,16 +1,22 @@
// RUN: xdsl-opt %s | xdsl-opt --print-op-generic | filecheck %s
// RUN: xdsl-opt %s | xdsl-opt --print-op-generic | xdsl-opt | filecheck %s
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'm not sure of the benefit of three xdsl-opts

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

For around-tripping printing and parsing of both generic and custom syntax.


// CHECK: module
"builtin.module"() ({
"func.func"() ({
// CHECK: %0 = "arith.constant"() {"value" = 0 : i64} : () -> i64
// CHECK: %0 = arith.constant 0 : i64
%0 = "arith.constant"() {"value" = 0 : i64} : () -> i64
// CHECK: %1 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> f32
// CHECK: %1 = builtin.unrealized_conversion_cast %0 : i64 to f32
%1 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> f32
// CHECK: %2 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> i32
// CHECK: %2 = builtin.unrealized_conversion_cast %0 : i64 to i32
%2 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> i32
// CHECK: %3 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> i64
// CHECK: %3 = builtin.unrealized_conversion_cast %0 : i64 to i64
%3 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> i64
// CHECK: %4 = builtin.unrealized_conversion_cast to i64 {"comment" = "test"}
%4 = "builtin.unrealized_conversion_cast"() {"comment" = "test"} : () -> i64
// CHECK: %5 = builtin.unrealized_conversion_cast %0, %0 : i64, i64 to f32
%5 = "builtin.unrealized_conversion_cast"(%0, %0) : (i64, i64) -> f32
// CHECK: %6, %7 = builtin.unrealized_conversion_cast %5 : f32 to i64, i64
%6, %7 = "builtin.unrealized_conversion_cast"(%5) : (f32) -> (i64, i64)
"func.return"() : () -> ()
}) {"function_type" = () -> (), "sym_name" = "builtin"} : () -> ()
}) : () -> ()
27 changes: 27 additions & 0 deletions tests/filecheck/mlir-conversion/with-mlir/unrealized_conv_cast.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
// RUN: xdsl-opt %s | mlir-opt --allow-unregistered-dialect | filecheck %s

"builtin.module"() ({
"func.func"() ({
%0 = "arith.constant"() {"value" = 0 : i64} : () -> i64
%1 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> f32
%2 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> i32
%3 = "builtin.unrealized_conversion_cast"(%0) : (i64) -> i64
%4 = "builtin.unrealized_conversion_cast"() {"comment" = "test"} : () -> i64
%5 = "builtin.unrealized_conversion_cast"(%0, %0) : (i64, i64) -> f32
%6, %7 = "builtin.unrealized_conversion_cast"(%5) : (f32) -> (i64, i64)
"func.return"() : () -> ()
}) {"function_type" = () -> (), "sym_name" = "builtin"} : () -> ()
}) : () -> ()

// CHECK: module {
// CHECK-NEXT: func.func @builtin() {
// CHECK-NEXT: %c0_i64 = arith.constant 0 : i64
// CHECK-NEXT: %0 = builtin.unrealized_conversion_cast %c0_i64 : i64 to f32
// CHECK-NEXT: %1 = builtin.unrealized_conversion_cast %c0_i64 : i64 to i32
// CHECK-NEXT: %2 = builtin.unrealized_conversion_cast %c0_i64 : i64 to i64
// CHECK-NEXT: %3 = builtin.unrealized_conversion_cast to i64 {comment = "test"}
// CHECK-NEXT: %4 = builtin.unrealized_conversion_cast %c0_i64, %c0_i64 : i64, i64 to f32
// CHECK-NEXT: %5:2 = builtin.unrealized_conversion_cast %4 : f32 to i64, i64
// CHECK-NEXT: return
// CHECK-NEXT: }
// CHECK-NEXT: }
8 changes: 4 additions & 4 deletions tests/filecheck/transforms/convert-stencil-to-ll-mlir-tiled.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -575,12 +575,12 @@ builtin.module {

// CHECK-NEXT: func.func @apply_kernel(%226 : memref<15x15xf32>, %227 : memref<15x15xf32>, %timers : !llvm.ptr<f64>) attributes {"param_names" = ["u_vec_0", "u_vec_1", "timers"]}{
// CHECK-NEXT: %228 = "gpu.alloc"() {"operand_segment_sizes" = array<i32: 0, 0, 0>} : () -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_1 = "builtin.unrealized_conversion_cast"(%228) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %229 = "builtin.unrealized_conversion_cast"(%227) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_1 = builtin.unrealized_conversion_cast %228 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: %229 = builtin.unrealized_conversion_cast %227 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: "gpu.memcpy"(%228, %229) {"operand_segment_sizes" = array<i32: 0, 1, 1>} : (memref<15x15xf32>, memref<15x15xf32>) -> ()
// CHECK-NEXT: %230 = "gpu.alloc"() {"operand_segment_sizes" = array<i32: 0, 0, 0>} : () -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_0 = "builtin.unrealized_conversion_cast"(%230) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %231 = "builtin.unrealized_conversion_cast"(%226) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_0 = builtin.unrealized_conversion_cast %230 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: %231 = builtin.unrealized_conversion_cast %226 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: "gpu.memcpy"(%230, %231) {"operand_segment_sizes" = array<i32: 0, 1, 1>} : (memref<15x15xf32>, memref<15x15xf32>) -> ()
// CHECK-NEXT: %time_m_1 = arith.constant 0 : index
// CHECK-NEXT: %time_M_1 = arith.constant 10 : index
Expand Down
8 changes: 4 additions & 4 deletions tests/filecheck/transforms/convert-stencil-to-ll-mlir.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -439,12 +439,12 @@ builtin.module {

// CHECK-NEXT: func.func @apply_kernel(%146 : memref<15x15xf32>, %147 : memref<15x15xf32>, %timers : !llvm.ptr<f64>) attributes {"param_names" = ["u_vec_0", "u_vec_1", "timers"]}{
// CHECK-NEXT: %148 = "gpu.alloc"() {"operand_segment_sizes" = array<i32: 0, 0, 0>} : () -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_1 = "builtin.unrealized_conversion_cast"(%148) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %149 = "builtin.unrealized_conversion_cast"(%147) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_1 = builtin.unrealized_conversion_cast %148 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: %149 = builtin.unrealized_conversion_cast %147 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: "gpu.memcpy"(%148, %149) {"operand_segment_sizes" = array<i32: 0, 1, 1>} : (memref<15x15xf32>, memref<15x15xf32>) -> ()
// CHECK-NEXT: %150 = "gpu.alloc"() {"operand_segment_sizes" = array<i32: 0, 0, 0>} : () -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_0 = "builtin.unrealized_conversion_cast"(%150) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %151 = "builtin.unrealized_conversion_cast"(%146) : (memref<15x15xf32>) -> memref<15x15xf32>
// CHECK-NEXT: %u_vec_0 = builtin.unrealized_conversion_cast %150 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: %151 = builtin.unrealized_conversion_cast %146 : memref<15x15xf32> to memref<15x15xf32>
// CHECK-NEXT: "gpu.memcpy"(%150, %151) {"operand_segment_sizes" = array<i32: 0, 1, 1>} : (memref<15x15xf32>, memref<15x15xf32>) -> ()
// CHECK-NEXT: %time_m_1 = arith.constant 0 : index
// CHECK-NEXT: %time_M_1 = arith.constant 10 : index
Expand Down
10 changes: 5 additions & 5 deletions tests/filecheck/transforms/reconcile_unrealized_casts.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ builtin.module {
}

// CHECK-NEXT: func.func @failure_simple_cast(%{{.*}} : i64) -> i32 {
// CHECK-NEXT: %3 = "builtin.unrealized_conversion_cast"(%{{.*}}) : (i64) -> i32
// CHECK-NEXT: %3 = builtin.unrealized_conversion_cast %{{.*}} : i64 to i32
// CHECK-NEXT: func.return %3 : i32
// CHECK-NEXT: }

Expand All @@ -85,8 +85,8 @@ builtin.module {
}

// CHECK-NEXT: func.func @failure_chain(%{{.*}} : i64) -> i32 {
// CHECK-NEXT: %4 = "builtin.unrealized_conversion_cast"(%{{.*}}) : (i64) -> i1
// CHECK-NEXT: %5 = "builtin.unrealized_conversion_cast"(%4) : (i1) -> i32
// CHECK-NEXT: %4 = builtin.unrealized_conversion_cast %{{.*}} : i64 to i1
// CHECK-NEXT: %5 = builtin.unrealized_conversion_cast %4 : i1 to i32
// CHECK-NEXT: func.return %5 : i32
// CHECK-NEXT: }

Expand Down Expand Up @@ -114,8 +114,8 @@ builtin.module {
}

// CHECK-NEXT: func.func @mismatch_size_cast_use(%{{.*}} : i64, %{{.*}} : i64) -> i64 {
// CHECK-NEXT: %7, %8 = "builtin.unrealized_conversion_cast"(%{{.*}}, %{{.*}}) : (i64, i64) -> (i16, i16)
// CHECK-NEXT: %9 = "builtin.unrealized_conversion_cast"(%7) : (i16) -> i1
// CHECK-NEXT: %7, %8 = builtin.unrealized_conversion_cast %{{.*}}, %{{.*}} : i64, i64 to i16, i16
// CHECK-NEXT: %9 = builtin.unrealized_conversion_cast %7 : i16 to i1
// CHECK-NEXT: %10 = "test.op"(%9, %9) : (i1, i1) -> i64
// CHECK-NEXT: func.return %10 : i64
// CHECK-NEXT: }
Expand Down
38 changes: 38 additions & 0 deletions xdsl/dialects/builtin.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,8 @@
overload,
)

from typing_extensions import Self

from xdsl.ir import (
Attribute,
AttributeCovT,
Expand Down Expand Up @@ -1109,6 +1111,42 @@ def get(inputs: Sequence[SSAValue | Operation], result_type: Sequence[Attribute]
result_types=[result_type],
)

@classmethod
def parse(cls, parser: Parser) -> Self:
if parser.parse_optional_characters("to") is None:
args = parser.parse_comma_separated_list(
parser.Delimiter.NONE,
parser.parse_unresolved_operand,
)
parser.parse_punctuation(":")
input_types = parser.parse_comma_separated_list(
parser.Delimiter.NONE,
parser.parse_type,
)
parser.parse_characters("to")
inputs = parser.resolve_operands(args, input_types, parser.pos)
else:
inputs = list[SSAValue]()
output_types = parser.parse_comma_separated_list(
parser.Delimiter.NONE,
parser.parse_type,
)
attributes = parser.parse_optional_attr_dict()
return UnrealizedConversionCastOp([inputs], [output_types], attributes)

def print(self, printer: Printer):
def print_fn(operand: SSAValue) -> None:
return printer.print_attribute(operand.type)

if self.inputs:
printer.print(" ")
printer.print_list(self.inputs, printer.print_operand)
printer.print_string(" : ")
printer.print_list(self.inputs, print_fn)
printer.print_string(" to ")
printer.print_list(self.outputs, print_fn)
printer.print_op_attributes(self.attributes)


class UnregisteredOp(IRDLOperation, ABC):
"""
Expand Down