This PR adds all the instructions in the RV32I/RV64I Section 2.8
(Control and Status Register Instructions) of the spec.

WIP: this section of the spec defines instructions with weird behavior,
like:

> Atomically swaps values in the CSRs and integer registers. CSRRW reads
the old value of the CSR, zero-extends the value to XLEN bits, then
writes it to integer register rd. The initial value in rs1 is written to
the CSR. The initial value in rs1 is written to the CSR. **If rd=x0,
then the instruction shall not read the CSR and shall not cause any of
the side-effects that might occur on a CSR read.**

In order to expose this *full* (e.g.: *read/write*) VS *limited* (e.g.:
*write only*) behavior the idea is to treat instructions like regular
ones by taking into account their *full* behaviour and then use an
attribute to switch on the *limited* mode. When, for example, we have a
`riscv.csrrw` in *limited mode*, rd **must be allocated to x0**.

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Co-authored-by: Sasha Lopoukhine <superlopuh@gmail.com>