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[WIP] RISCV Register Allocator
Alban Dutilleul edited this page May 23, 2023
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The initial plan is to accommodate the allocation of N SSAValues and leave the rest to RiscEmu (in decreasing concreteness/detail and order subject to change):
- Allow the use of N SSAValues to be regalloc'ed in both RiscEmu and current regalloc in xDSL
- Identify test cases for end-to-end operation (use LLVM test suite and/or manually compiled examples
- Expand the codegen for the Toy language to be able to generate more complex test cases (nested expressions, maybe lowering from arith?, branching?)
- Implement a linear scan allocation scheme using elementary live intervals (i.e., bottom to top of code block)
- Expand this to simple branching code
- Look into graph colouring and more nuance to register allocation scheme