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Some VT-d IOMMUs are non-coherent, which requires a cache write back in order for the changes made by the CPU to be visible to the IOMMU. This cache write back was unconditionally done using clflush, but there are other more efficient instructions to do so, hence implement support for them using the alternative framework. This is part of XSA-321. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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