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xen: add files needed for minimal riscv build
Add arch-specific makefiles and configs needed to build for riscv. Also add a minimal head.S that is a simple infinite loop. head.o can be built with $ make XEN_TARGET_ARCH=riscv64 SUBSYSTEMS=xen -C xen tiny64_defconfig $ make XEN_TARGET_ARCH=riscv64 SUBSYSTEMS=xen -C xen TARGET=riscv64/head.o No other TARGET is supported at the moment. Signed-off-by: Connor Davis <connojdavis@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bobby Eshleman <bobbyeshleman@gmail.com>
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CONFIG_RISCV := y | ||
CONFIG_RISCV_64 := y | ||
CONFIG_RISCV_$(XEN_OS) := y | ||
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CONFIG_XEN_INSTALL_SUFFIX := |
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config RISCV | ||
def_bool y | ||
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config RISCV_64 | ||
def_bool y | ||
select 64BIT | ||
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config ARCH_DEFCONFIG | ||
string | ||
default "arch/riscv/configs/tiny64_defconfig" | ||
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menu "Architecture Features" | ||
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source "arch/Kconfig" | ||
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endmenu | ||
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menu "ISA Selection" | ||
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choice | ||
prompt "Base ISA" | ||
default RISCV_ISA_RV64IMA if RISCV_64 | ||
help | ||
This selects the base ISA extensions that Xen will target. | ||
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config RISCV_ISA_RV64IMA | ||
bool "RV64IMA" | ||
help | ||
Use the RV64I base ISA, plus the "M" and "A" extensions | ||
for integer multiply/divide and atomic instructions, respectively. | ||
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endchoice | ||
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config RISCV_ISA_C | ||
bool "Compressed extension" | ||
default y | ||
help | ||
Add "C" to the ISA subsets that the toolchain is allowed to | ||
emit when building Xen, which results in compressed instructions | ||
in the Xen binary. | ||
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If unsure, say Y. | ||
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endmenu | ||
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source "common/Kconfig" | ||
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source "drivers/Kconfig" |
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.PHONY: include | ||
include: |
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######################################## | ||
# RISCV-specific definitions | ||
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CFLAGS-$(CONFIG_RISCV_64) += -mabi=lp64 | ||
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riscv-march-$(CONFIG_RISCV_ISA_RV64IMA) := rv64ima | ||
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c | ||
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# Note that -mcmodel=medany is used so that Xen can be mapped | ||
# into the upper half _or_ the lower half of the address space. | ||
# -mcmodel=medlow would force Xen into the lower half. | ||
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CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany | ||
CFLAGS += -I$(BASEDIR)/include |
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# CONFIG_SCHED_CREDIT is not set | ||
# CONFIG_SCHED_RTDS is not set | ||
# CONFIG_SCHED_NULL is not set | ||
# CONFIG_SCHED_ARINC653 is not set | ||
# CONFIG_TRACEBUFFER is not set | ||
# CONFIG_HYPFS is not set | ||
# CONFIG_GRANT_TABLE is not set | ||
# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set | ||
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CONFIG_RISCV_64=y | ||
CONFIG_DEBUG=y | ||
CONFIG_DEBUG_INFO=y | ||
CONFIG_EXPERT=y |
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#include <asm/config.h> | ||
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.text | ||
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ENTRY(start) | ||
j start |
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#ifndef __RISCV_CONFIG_H__ | ||
#define __RISCV_CONFIG_H__ | ||
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#if defined(CONFIG_RISCV_64) | ||
# define LONG_BYTEORDER 3 | ||
# define ELFSIZE 64 | ||
# define MAX_VIRT_CPUS 128u | ||
#else | ||
# error "Unsupported RISCV variant" | ||
#endif | ||
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#define BYTES_PER_LONG (1 << LONG_BYTEORDER) | ||
#define BITS_PER_LONG (BYTES_PER_LONG << 3) | ||
#define POINTER_ALIGN BYTES_PER_LONG | ||
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#define BITS_PER_LLONG 64 | ||
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/* xen_ulong_t is always 64 bits */ | ||
#define BITS_PER_XEN_ULONG 64 | ||
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#define CONFIG_RISCV_L1_CACHE_SHIFT 6 | ||
#define CONFIG_PAGEALLOC_MAX_ORDER 18 | ||
#define CONFIG_DOMU_MAX_ORDER 9 | ||
#define CONFIG_HWDOM_MAX_ORDER 10 | ||
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#define OPT_CONSOLE_STR "dtuart" | ||
#define INVALID_VCPU_ID MAX_VIRT_CPUS | ||
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/* Linkage for RISCV */ | ||
#ifdef __ASSEMBLY__ | ||
#define ALIGN .align 2 | ||
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#define ENTRY(name) \ | ||
.globl name; \ | ||
ALIGN; \ | ||
name: | ||
#endif | ||
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#endif /* __RISCV_CONFIG_H__ */ | ||
/* | ||
* Local variables: | ||
* mode: C | ||
* c-file-style: "BSD" | ||
* c-basic-offset: 4 | ||
* indent-tabs-mode: nil | ||
* End: | ||
*/ |