LoongArch: fix wrong patterns involving sign-extension insns (take 2)

xen0n · Feb 7, 2022 · 23231e3 · chenglulu326 · Feb 7, 2022 · xen0n
1 parent 5072a3c
commit 23231e3
Showing 1 changed file with 0 additions and 27 deletions.
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
@@ -1381,33 +1381,6 @@
   [(set_attr "move_type" "signext,load")
    (set_attr "mode" "SI")])
 
-(define_insn "*extenddi_truncate<mode>"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI
-	    (truncate:SHORT (match_operand:DI 1 "register_operand" "r"))))]
-  "TARGET_64BIT"
-  "ext.w.<size>\t%0,%1"
-  [(set_attr "move_type" "signext")
-   (set_attr "mode" "DI")])
-
-(define_insn "*extendsi_truncate<mode>"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI
-	    (truncate:SHORT (match_operand:DI 1 "register_operand" "r"))))]
-  "TARGET_64BIT"
-  "ext.w.<size>\t%0,%1"
-  [(set_attr "move_type" "signext")
-   (set_attr "mode" "SI")])
-
-(define_insn "*extendhi_truncateqi"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI
-	    (truncate:QI (match_operand:DI 1 "register_operand" "r"))))]
-  "TARGET_64BIT"
-  "ext.w.<size>\t%0,%1"
-  [(set_attr "move_type" "signext")
-   (set_attr "mode" "SI")])
-
 (define_insn "extendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]