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BLD: a few XL compiler observations #2333
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I'm not certain exactly what patches you are trying. "v" and "wa" register constraints are not interchangeable. I don't know what XLC supports. Originally there were the Altivec/VMX registers ("v"). Then Power added VSX registers, which combine the VMX registers with the FP registers. The mnemonics for both original register files started with 0 and only one could win for retaining the meaning of 0: the VRs or the FPRs. "v" emits the appropriate register numbers for Altivec instructions and "wa" emits the appropriate register numbers for VSX instructions. Altivec and VSX instructions can be intermingled, but one must use the appropriate subset of 32 Altivec-only registers and one must adjust the register numbers by 32, depending on the instruction. The 0(4) and 0(6) don't make any sense in that context. Those normally would be displacement addresses, or indirect addresses in this case because the "0" means displacement 0. "0(4)" would represent 0 displacement relative to register 4. But the instructions are not loads or stores, so an address operand is completely wrong. Something must be using the completely wrong output template in inlined assembly to emit an address where a plain register should appear. |
Could you supply full patch that breaks the build for you? |
The patch file is below (from Without the patch I got assembly complaints that have been described in the previous issues linked above. I can get you more detailed log files if those are helpful. |
The confused assembly comes from the srot_microk_power8.c included by srot.c, which has
etc. starting from line 107, suggesting there is something wrong with the contents of %x11 and %x12. (srot_microk_power8.c was basically rewritten by Alan Modra in #1078 , I only applied the patch he submitted) |
First, please don't change the code to allow it to support XLC. One should not limit the registers to Altivec/VMX because of XLC bugs. Second, I have no idea if XLC implements the '%x' output format correctly. XLC is completely the wrong priority. Please stop any activities to accommodate XLC. |
Ok, I was just confirming that this roadblock seems reasonable/still exists. Sounds like it is still a blocker. I think we have a way to communicate with the XL compiler team from LANL so I'll see if the group wants to ask the IBM folks about that later this week. Thanks! |
I know we're not "supposed" to patch OpenBLAS code to work with XLC on POWER9 because those are mostly issues with the compiler/toolchain upstream rather than with OpenBLAS, as previously noted in a few places (by i.e., @edelsohn ).
Nonetheless, I tried to apply some of the hints on registers from #1699 and #1078 (comment).
I'm doing the build in a spack-based context, and after applying the various
vs32
->v0
and=wa
->=v
substitutions there seems to be some assembly-related choking, which is perhaps not surprising, but just to report an example of it using latest OpenBLAS develop branch:The problem lines (i.e., 102, 103, 110, 111 shown below & complained about above) from
srot_k$1.s
always seem to have parentheses:That's way over my head, but anyway just passing along in case it is helpful or if there are things you'd like me to try there. I did mess around with
COMMON_OPT=-mcpu=power9 -mtune=power9 -Ofast
and an emptyCOMMON_OPT
to get the same result using spack's build system.cc @AndrewGaspar @gshipman @junghans
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