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Partitioning Vitis AI SubGraphs on CPU/DPU - EnvironmentNotWritableError #85

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nhphuong91 opened this issue Jun 23, 2021 · 4 comments
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@nhphuong91
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Hi, I'm following Partitioning Vitis AI SubGraphs on CPU/DPU tutorial but stuck at the Install Packages and Patches on the Vitis AI Tools Container step. See screenshot below:
image

(vitis-ai-pytorch) Vitis-AI /workspace/packages > conda install unilog-1.3.2-h7b12538_35.tar.bz2

Downloading and Extracting Packages
######################################################################################################################## | 100%
Preparing transaction: done
Verifying transaction: failed

EnvironmentNotWritableError: The current user does not have write permissions to the target environment.
environment location: /opt/vitis_ai/conda/envs/vitis-ai-pytorch
uid: 1020
gid: 1023

Can anyone support me with it? Thanks in advanced!

@Premduth
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@nhphuong91 can you try this in the new tutorials in https://github.com/Xilinx/Vitis-AI-Tutorials. If it is still not working there, open the issue there and close this one

@nhphuong91
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@Premduth Thanks but I found that the Partitioning Vitis AI SubGraphs on CPU/DPU tutorial no longer exist on that new repo

@Premduth
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@nhphuong91 can you add this comment to the https://github.com/Xilinx/Vitis-AI-Tutorials? Someone there can comment on the status. Not sure why that would not be there anymore

@Premduth
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Closing out this one to open in https://github.com/Xilinx/Vitis-AI-Tutorials so the right people can answer

vmayoral pushed a commit to vmayoral/Vitis-Tutorials that referenced this issue Jan 20, 2022
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
695eee4 update version
04f4d5f fix typos
64588a9 update version
b763a17 update RTM 3D forward test
1773e6e Merge pull request Xilinx#90 from changg/fix_time
eee98af fix time
4953200 Merge pull request Xilinx#89 from yuanqian/next
dd4a215 increase max time
8b66520 Merge pull request Xilinx#88 from yuanqian/next
b1c2661 increase memory due to memory limit in daily regression
2b1e855 Merge pull request Xilinx#87 from yuanqian/next
e8cc376 increase max memory in runtime
ee272e1 increase maxruntime
134abba Merge pull request Xilinx#86 from liyuanz/next
3aa7fd8 fix bug about LD_LIBRARY_PATH in utils.mk
5f047f8 Merge pull request Xilinx#85 from liyuanz/next
956cd0b fix CR about Linking XRT native API on CentOS 8 fails

Co-authored-by: sdausr <sdausr@xilinx.com>

have 100% pass rate in daily regression
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
b8aa0ac Merge pull request Xilinx#98 from changg/round2-mk
0dafa9e fix
69ce1de Merge pull request Xilinx#97 from changg/round2-mk
33635fb fix utils.mk
bb09f85 Merge pull request Xilinx#96 from tuol/fix_cr_1125397
26bfd12 upate description.json for GUI
6142bf4 Merge pull request Xilinx#95 from tuol/fix_cr1110852
18b6b69 add description for cscmvSingleHBM
489d6fe Merge pull request Xilinx#94 from changg/wa_u280
c83ed11 WA for u280
70d666c Revert "wa for xilinx_u280_xdma_201920_3"
27306c5 Merge pull request Xilinx#93 from changg/wa_u280_2019
2b4ec88 wa for xilinx_u280_xdma_201920_3
af1d094 Merge pull request Xilinx#92 from liyuanz/replace_cflags
a9ff957 replace cflags with clflags
eb58a83 Merge pull request Xilinx#91 from tuol/fix_cr_1110852
c9ca9ab add description to L2/tests/cscmvSingleHbm
b8e0210 Merge pull request Xilinx#90 from tuol/fix_cr_1083211
75204c8 remove 'exclude' from description.json
965b2e0 Merge pull request Xilinx#88 from liyuanz/replace_blacklist
0e87eee replace whiltelist/blacklist to allowlist/blocklist
ad26de7 Merge pull request Xilinx#87 from liyuanz/next
3db258c increase time
def14fe Merge pull request Xilinx#85 from changg/add_extraflags
f8a6122 fix makefile
031de2c Merge pull request Xilinx#84 from liyuanz/next
f10953c increase time
4745f24 Merge pull request Xilinx#83 from changg/fix_utils
6fb2652 fix utisl
7d9278f Merge pull request Xilinx#82 from liyuanz/replace_targets
c1c2de5 update targes
68ae52e Merge pull request Xilinx#80 from changg/metadata
6225d51 draft metadata files
e74cf2b change 2021.2_stable_latest to 2022.1_stable_latest

Co-authored-by: sdausr <sdausr@xilinx.com>
CRTejaswi pushed a commit to CRTejaswi/amd-vitis that referenced this issue Oct 3, 2023
b0ee140 Merge pull request Xilinx#92 from liyuanz/add_mmm
db0107b update
1a68c39 Merge pull request Xilinx#91 from liyuanz/add_mm
533e836 update
ab8f933 Merge pull request Xilinx#90 from tianminr/readme_modification
b99355a update readme
ba67162 Merge pull request Xilinx#89 from tianminr/doc
0c1f13d update api.json
8845ce5 Merge pull request Xilinx#88 from tianminr/doc
25561cf refine docs
5d55ecf Merge pull request Xilinx#87 from tianminr/plane_wave_refine
74da1b7 fixed for json file and coding-style
daff5ca Merge remote-tracking branch 'xf_ultrasound/next' into plane_wave_refine
0714894 Merge pull request Xilinx#86 from tianminr/code_clean
ba7d629 refine planewave regression
c353e1c clean for old window apis
23ede93 Merge pull request Xilinx#85 from tianminr/regression_refine
9af26a9 modificaiton for docson 23.1
8d81605 scanline timing update
d98d78e regression refine
e75b377 Merge pull request Xilinx#84 from tianminr/next_clean
b5fa450 clean kernels.hpp
fdafd55 next branch clean

Co-authored-by: sdausr <sdausr@xilinx.com>
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