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fix(rtc): adding argument for pac registers
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@lucasbrendel
lucasbrendel committed Dec 26, 2023
1 parent 476d857 commit d689e08
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Showing 3 changed files with 81 additions and 100 deletions.
17 changes: 4 additions & 13 deletions Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -22,21 +22,12 @@ xmc4400 = { version = "0.8.2", optional = true }
xmc4500 = { version = "0.8.2", optional = true }
xmc4700 = { version = "0.8.2", optional = true }
xmc4800 = { version = "0.7.2", optional = true }
cortex-m = "0.7.7"
cortex-m = {version = "0.7.7", features = ['critical-section-single-core']}
nb = "1.1.0"
cortex-m-rt = "0.7.3"

[dependencies.void]
default-features = false
version = "1.0.2"

[dependencies.cast]
default-features = false
version = "0.3.0"

[dependencies.embedded-hal]
features = ["unproven"]
version = "0.2.7"
void = { version = "1.0.2", default-features = false }
cast = { version = "0.3.0", default-features = false }
embedded-hal = { version = "0.2.7", features = ["unproven"] }

[features]
device-selected = []
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19 changes: 10 additions & 9 deletions examples/rtc.rs
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Original file line number Diff line number Diff line change
@@ -1,18 +1,19 @@
#![no_main]
#![no_std]
#![no_main]

#[allow(unused)]
use panic_halt;

use hal::rtc;
use xmc4_hal as hal;

extern crate panic_semihosting;
use cortex_m_rt::entry;
use hal::pac;
use xmc4_hal as hal;

#[entry]
fn main() -> ! {
let r = rtc::Rtc::new();
r.start();
let p = pac::Peripherals::take().unwrap();
let rtc = hal::rtc::Rtc::new(p.RTC);

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Diff in /home/runner/work/xmc4-hal/xmc4-hal/examples/rtc.rs
rtc.enable();


loop {
continue;
}
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145 changes: 67 additions & 78 deletions src/rtc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -178,21 +178,23 @@ pub enum WakeupEvent {
Years,
}

pub trait RtcExt {
fn constrain(self) -> Rtc;
// pub trait RtcExt {
// fn constrain(self) -> Rtc;
// }

// impl RtcExt for RTC {
// fn constrain(self) -> Rtc {
// Rtc {}
// }
// }

pub struct Rtc {
pub regs: RTC,
}

impl RtcExt for RTC {
fn constrain(self) -> Rtc {
Rtc {}
}
}

pub struct Rtc {}

impl Rtc {
pub fn new() -> Self {
Rtc {}
pub fn new(rtc: RTC) -> Self {
Self { regs: rtc }
}

#[inline(always)]
Expand All @@ -205,27 +207,24 @@ impl Rtc {

pub fn start(&self) {
self.wait_for_mirrsts();
unsafe {
let _ = &(*RTC::ptr()).ctr().write(|w| w.enb().set_bit());
}
self.regs.ctr().write(|w| w.enb().set_bit());
}

pub fn stop(&self) {
self.wait_for_mirrsts();
unsafe {
let _ = &(*RTC::ptr()).ctr().write(|w| w.enb().clear_bit());
}
self.regs.ctr().write(|w| w.enb().clear_bit());
}

pub fn is_running(&self) -> bool {
self.wait_for_mirrsts();
let rtc = unsafe { &*RTC::ptr() };
rtc.ctr().read().enb().bit_is_set()
self.regs.ctr().read().enb().bit_is_set()
}

pub fn set_prescaler(&self, prescaler: u16) {
self.wait_for_mirrsts();
set_field!(RTC, ctr, div, prescaler);
self.regs
.ctr()
.write(|w| unsafe { w.div().bits(prescaler) });
}

pub fn set_time(&self, time: Time) {
Expand All @@ -236,31 +235,29 @@ impl Rtc {
assert!(time.year < MAX_YEAR);

self.wait_for_mirrsts();
let rtc = periph!(RTC);
rtc.tim0().modify(|_, w| unsafe {
self.regs.tim0().modify(|_, w| unsafe {
w.se().bits(time.second);
w.mi().bits(time.minute);
w.ho().bits(time.hour);
w.da().bits(time.day)
});
self.wait_for_mirrsts();
rtc.tim1().modify(|_, w| unsafe {
self.regs.tim1().modify(|_, w| unsafe {
w.dawe().bits(time.weekday as u8);
w.mo().bits(time.month as u8);
w.ye().bits(time.year)
});
}

pub fn get_time(&self) -> Time {
let rtc = periph!(RTC);
Time {
second: rtc.tim0().read().se().bits(),
minute: rtc.tim0().read().mi().bits(),
hour: rtc.tim0().read().ho().bits(),
day: rtc.tim0().read().da().bits(),
weekday: Weekday::from(rtc.tim1().read().dawe().bits()),
month: Month::from(rtc.tim1().read().mo().bits()),
year: rtc.tim1().read().ye().bits(),
second: self.regs.tim0().read().se().bits(),
minute: self.regs.tim0().read().mi().bits(),
hour: self.regs.tim0().read().ho().bits(),
day: self.regs.tim0().read().da().bits(),
weekday: Weekday::from(self.regs.tim1().read().dawe().bits()),
month: Month::from(self.regs.tim1().read().mo().bits()),
year: self.regs.tim1().read().ye().bits(),
}
}

Expand All @@ -286,30 +283,28 @@ impl Rtc {
assert!(time.year < MAX_YEAR);

self.wait_for_mirrsts();
let rtc = periph!(RTC);
rtc.atim0().modify(|_, w| unsafe {
self.regs.atim0().modify(|_, w| unsafe {
w.ase().bits(time.second);
w.ami().bits(time.minute);
w.aho().bits(time.hour);
w.ada().bits(time.day)
});
self.wait_for_mirrsts();
rtc.atim1().modify(|_, w| unsafe {
self.regs.atim1().modify(|_, w| unsafe {
w.amo().bits(time.month as u8);
w.aye().bits(time.year)
});
}

pub fn get_alarm(&self) -> Time {
let rtc = periph!(RTC);
Time {
second: rtc.atim0().read().ase().bits(),
minute: rtc.atim0().read().ami().bits(),
hour: rtc.atim0().read().aho().bits(),
day: rtc.atim0().read().ada().bits(),
second: self.regs.atim0().read().ase().bits(),
minute: self.regs.atim0().read().ami().bits(),
hour: self.regs.atim0().read().aho().bits(),
day: self.regs.atim0().read().ada().bits(),
weekday: Weekday::Sunday,
month: Month::from(rtc.atim1().read().amo().bits()),
year: rtc.atim1().read().aye().bits(),
month: Month::from(self.regs.atim1().read().amo().bits()),
year: self.regs.atim1().read().aye().bits(),
}
}

Expand All @@ -328,8 +323,7 @@ impl Rtc {
}

pub fn get_event_status(&self) -> u32 {
let read = unsafe { &(*RTC::ptr()).stssr().read() };
read.bits()
self.regs.stssr().read().bits()
}

pub fn enable(&self) {
Expand All @@ -349,119 +343,114 @@ impl Rtc {

fn enable_event(&self, event: Event) {
let general = unsafe { &*SCU_GENERAL::ptr() };
let rtc = unsafe { &*RTC::ptr() };
while general.mirrsts().read().rtc_msksr().bit_is_set() {}
match event {
Event::Seconds => {
rtc.msksr().write(|w| w.mpse().set_bit());
self.regs.msksr().write(|w| w.mpse().set_bit());
}
Event::Minutes => {
rtc.msksr().write(|w| w.mpmi().set_bit());
self.regs.msksr().write(|w| w.mpmi().set_bit());
}
Event::Hours => {
rtc.msksr().write(|w| w.mpho().set_bit());
self.regs.msksr().write(|w| w.mpho().set_bit());
}
Event::Days => {
rtc.msksr().write(|w| w.mpda().set_bit());
self.regs.msksr().write(|w| w.mpda().set_bit());
}
Event::Months => {
rtc.msksr().write(|w| w.mpmo().set_bit());
self.regs.msksr().write(|w| w.mpmo().set_bit());
}
Event::Years => {
rtc.msksr().write(|w| w.mpye().set_bit());
self.regs.msksr().write(|w| w.mpye().set_bit());
}
Event::Alarm => {
rtc.msksr().write(|w| w.mai().set_bit());
self.regs.msksr().write(|w| w.mai().set_bit());
}
};
}

fn disable_event(&self, event: Event) {
let general = unsafe { &*SCU_GENERAL::ptr() };
let rtc = unsafe { &*RTC::ptr() };
while general.mirrsts().read().rtc_msksr().bit_is_set() {}
match event {
Event::Seconds => {
rtc.msksr().write(|w| w.mpse().clear_bit());
self.regs.msksr().write(|w| w.mpse().clear_bit());
}
Event::Minutes => {
rtc.msksr().write(|w| w.mpmi().clear_bit());
self.regs.msksr().write(|w| w.mpmi().clear_bit());
}
Event::Hours => {
rtc.msksr().write(|w| w.mpho().clear_bit());
self.regs.msksr().write(|w| w.mpho().clear_bit());
}
Event::Days => {
rtc.msksr().write(|w| w.mpda().clear_bit());
self.regs.msksr().write(|w| w.mpda().clear_bit());
}
Event::Months => {
rtc.msksr().write(|w| w.mpmo().clear_bit());
self.regs.msksr().write(|w| w.mpmo().clear_bit());
}
Event::Years => {
rtc.msksr().write(|w| w.mpye().clear_bit());
self.regs.msksr().write(|w| w.mpye().clear_bit());
}
Event::Alarm => {
rtc.msksr().write(|w| w.mai().clear_bit());
self.regs.msksr().write(|w| w.mai().clear_bit());
}
};
}

fn clear_event(&self, event: Event) {

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let scu = unsafe { &(*SCU_GENERAL::ptr()) };
let rtc = unsafe { &*RTC::ptr() };
while scu.mirrsts().read().rtc_clrsr().bit_is_set() {}
rtc.clrsr().write(|w| unsafe { w.bits(u32::from(event)) });
self.regs.clrsr().write(|w| unsafe { w.bits(u32::from(event)) });
}

fn enable_hibernation_wake_up(&self, event: WakeupEvent) {
let rtc = unsafe { &*RTC::ptr() };
match event {
WakeupEvent::Alarm => {
rtc.ctr().write(|w| w.tae().set_bit());
self.regs.ctr().write(|w| w.tae().set_bit());
}
WakeupEvent::Seconds => {
rtc.ctr().write(|w| w.esec().set_bit());
self.regs.ctr().write(|w| w.esec().set_bit());
}
WakeupEvent::Minutes => {
rtc.ctr().write(|w| w.emic().set_bit());
self.regs.ctr().write(|w| w.emic().set_bit());
}
WakeupEvent::Hours => {
rtc.ctr().write(|w| w.ehoc().set_bit());
self.regs.ctr().write(|w| w.ehoc().set_bit());
}
WakeupEvent::Days => {
rtc.ctr().write(|w| w.edac().set_bit());
self.regs.ctr().write(|w| w.edac().set_bit());
}
WakeupEvent::Months => {
rtc.ctr().write(|w| w.emoc().set_bit());
self.regs.ctr().write(|w| w.emoc().set_bit());
}
WakeupEvent::Years => {
rtc.ctr().write(|w| w.eyec().set_bit());
self.regs.ctr().write(|w| w.eyec().set_bit());
}
};
}

fn disable_hibernation_wake_up(&self, event: WakeupEvent) {
let rtc = unsafe { &*RTC::ptr() };
match event {
WakeupEvent::Alarm => {
rtc.ctr().write(|w| w.tae().clear_bit());
self.regs.ctr().write(|w| w.tae().clear_bit());
}
WakeupEvent::Seconds => {
rtc.ctr().write(|w| w.esec().clear_bit());
self.regs.ctr().write(|w| w.esec().clear_bit());
}
WakeupEvent::Minutes => {
rtc.ctr().write(|w| w.emic().clear_bit());
self.regs.ctr().write(|w| w.emic().clear_bit());
}
WakeupEvent::Hours => {
rtc.ctr().write(|w| w.ehoc().clear_bit());
self.regs.ctr().write(|w| w.ehoc().clear_bit());
}
WakeupEvent::Days => {
rtc.ctr().write(|w| w.edac().clear_bit());
self.regs.ctr().write(|w| w.edac().clear_bit());
}
WakeupEvent::Months => {
rtc.ctr().write(|w| w.emoc().clear_bit());
self.regs.ctr().write(|w| w.emoc().clear_bit());
}
WakeupEvent::Years => {
rtc.ctr().write(|w| w.eyec().clear_bit());
self.regs.ctr().write(|w| w.eyec().clear_bit());
}
};
}
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