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rebuilding from new svd2rust (#41)
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@lucasbrendel
lucasbrendel committed Dec 29, 2022
1 parent a443646 commit e3c8e9c
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Showing 733 changed files with 40,614 additions and 134,871 deletions.
40 changes: 20 additions & 20 deletions src/can.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,68 +2,68 @@
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - CAN Clock Control Register"]
pub clc: crate::Reg<clc::CLC_SPEC>,
pub clc: CLC,
_reserved1: [u8; 0x04],
#[doc = "0x08 - Module Identification Register"]
pub id: crate::Reg<id::ID_SPEC>,
pub id: ID,
#[doc = "0x0c - CAN Fractional Divider Register"]
pub fdr: crate::Reg<fdr::FDR_SPEC>,
pub fdr: FDR,
_reserved3: [u8; 0xf0],
#[doc = "0x100..0x120 - List Register"]
pub list: [crate::Reg<list::LIST_SPEC>; 8],
pub list: [LIST; 8],
_reserved4: [u8; 0x20],
#[doc = "0x140..0x160 - Message Pending Register"]
pub mspnd: [crate::Reg<mspnd::MSPND_SPEC>; 8],
pub mspnd: [MSPND; 8],
_reserved5: [u8; 0x20],
#[doc = "0x180..0x1a0 - Message Index Register"]
pub msid: [crate::Reg<msid::MSID_SPEC>; 8],
pub msid: [MSID; 8],
_reserved6: [u8; 0x20],
#[doc = "0x1c0 - Message Index Mask Register"]
pub msimask: crate::Reg<msimask::MSIMASK_SPEC>,
pub msimask: MSIMASK,
#[doc = "0x1c4 - Panel Control Register"]
pub panctr: crate::Reg<panctr::PANCTR_SPEC>,
pub panctr: PANCTR,
#[doc = "0x1c8 - Module Control Register"]
pub mcr: crate::Reg<mcr::MCR_SPEC>,
pub mcr: MCR,
#[doc = "0x1cc - Module Interrupt Trigger Register"]
pub mitr: crate::Reg<mitr::MITR_SPEC>,
pub mitr: MITR,
}
#[doc = "CLC register accessor: an alias for `Reg<CLC_SPEC>`"]
#[doc = "CLC (rw) register accessor: an alias for `Reg<CLC_SPEC>`"]
pub type CLC = crate::Reg<clc::CLC_SPEC>;
#[doc = "CAN Clock Control Register"]
pub mod clc;
#[doc = "ID register accessor: an alias for `Reg<ID_SPEC>`"]
#[doc = "ID (r) register accessor: an alias for `Reg<ID_SPEC>`"]
pub type ID = crate::Reg<id::ID_SPEC>;
#[doc = "Module Identification Register"]
pub mod id;
#[doc = "FDR register accessor: an alias for `Reg<FDR_SPEC>`"]
#[doc = "FDR (rw) register accessor: an alias for `Reg<FDR_SPEC>`"]
pub type FDR = crate::Reg<fdr::FDR_SPEC>;
#[doc = "CAN Fractional Divider Register"]
pub mod fdr;
#[doc = "LIST register accessor: an alias for `Reg<LIST_SPEC>`"]
#[doc = "LIST (r) register accessor: an alias for `Reg<LIST_SPEC>`"]
pub type LIST = crate::Reg<list::LIST_SPEC>;
#[doc = "List Register"]
pub mod list;
#[doc = "MSPND register accessor: an alias for `Reg<MSPND_SPEC>`"]
#[doc = "MSPND (rw) register accessor: an alias for `Reg<MSPND_SPEC>`"]
pub type MSPND = crate::Reg<mspnd::MSPND_SPEC>;
#[doc = "Message Pending Register"]
pub mod mspnd;
#[doc = "MSID register accessor: an alias for `Reg<MSID_SPEC>`"]
#[doc = "MSID (r) register accessor: an alias for `Reg<MSID_SPEC>`"]
pub type MSID = crate::Reg<msid::MSID_SPEC>;
#[doc = "Message Index Register"]
pub mod msid;
#[doc = "MSIMASK register accessor: an alias for `Reg<MSIMASK_SPEC>`"]
#[doc = "MSIMASK (rw) register accessor: an alias for `Reg<MSIMASK_SPEC>`"]
pub type MSIMASK = crate::Reg<msimask::MSIMASK_SPEC>;
#[doc = "Message Index Mask Register"]
pub mod msimask;
#[doc = "PANCTR register accessor: an alias for `Reg<PANCTR_SPEC>`"]
#[doc = "PANCTR (rw) register accessor: an alias for `Reg<PANCTR_SPEC>`"]
pub type PANCTR = crate::Reg<panctr::PANCTR_SPEC>;
#[doc = "Panel Control Register"]
pub mod panctr;
#[doc = "MCR register accessor: an alias for `Reg<MCR_SPEC>`"]
#[doc = "MCR (rw) register accessor: an alias for `Reg<MCR_SPEC>`"]
pub type MCR = crate::Reg<mcr::MCR_SPEC>;
#[doc = "Module Control Register"]
pub mod mcr;
#[doc = "MITR register accessor: an alias for `Reg<MITR_SPEC>`"]
#[doc = "MITR (w) register accessor: an alias for `Reg<MITR_SPEC>`"]
pub type MITR = crate::Reg<mitr::MITR_SPEC>;
#[doc = "Module Interrupt Trigger Register"]
pub mod mitr;
136 changes: 21 additions & 115 deletions src/can/clc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -35,145 +35,52 @@ impl From<crate::W<CLC_SPEC>> for W {
}
}
#[doc = "Field `DISR` reader - Module Disable Request Bit"]
pub struct DISR_R(crate::FieldReader<bool, bool>);
impl DISR_R {
pub(crate) fn new(bits: bool) -> Self {
DISR_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DISR_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
pub type DISR_R = crate::BitReader<bool>;
#[doc = "Field `DISR` writer - Module Disable Request Bit"]
pub struct DISR_W<'a> {
w: &'a mut W,
}
impl<'a> DISR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
pub type DISR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLC_SPEC, bool, O>;
#[doc = "Field `DISS` reader - Module Disable Status Bit"]
pub struct DISS_R(crate::FieldReader<bool, bool>);
impl DISS_R {
pub(crate) fn new(bits: bool) -> Self {
DISS_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DISS_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
pub type DISS_R = crate::BitReader<bool>;
#[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
pub struct EDIS_R(crate::FieldReader<bool, bool>);
impl EDIS_R {
pub(crate) fn new(bits: bool) -> Self {
EDIS_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for EDIS_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
pub type EDIS_R = crate::BitReader<bool>;
#[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
pub struct EDIS_W<'a> {
w: &'a mut W,
}
impl<'a> EDIS_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
self.w
}
}
pub type EDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLC_SPEC, bool, O>;
#[doc = "Field `SBWE` writer - Module Suspend Bit Write Enable for OCDS"]
pub struct SBWE_W<'a> {
w: &'a mut W,
}
impl<'a> SBWE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
pub type SBWE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLC_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Module Disable Request Bit"]
#[inline(always)]
pub fn disr(&self) -> DISR_R {
DISR_R::new((self.bits & 0x01) != 0)
DISR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Module Disable Status Bit"]
#[inline(always)]
pub fn diss(&self) -> DISS_R {
DISS_R::new(((self.bits >> 1) & 0x01) != 0)
DISS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - Sleep Mode Enable Control"]
#[inline(always)]
pub fn edis(&self) -> EDIS_R {
EDIS_R::new(((self.bits >> 3) & 0x01) != 0)
EDIS_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Module Disable Request Bit"]
#[inline(always)]
pub fn disr(&mut self) -> DISR_W {
DISR_W { w: self }
#[must_use]
pub fn disr(&mut self) -> DISR_W<0> {
DISR_W::new(self)
}
#[doc = "Bit 3 - Sleep Mode Enable Control"]
#[inline(always)]
pub fn edis(&mut self) -> EDIS_W {
EDIS_W { w: self }
#[must_use]
pub fn edis(&mut self) -> EDIS_W<3> {
EDIS_W::new(self)
}
#[doc = "Bit 4 - Module Suspend Bit Write Enable for OCDS"]
#[inline(always)]
pub fn sbwe(&mut self) -> SBWE_W {
SBWE_W { w: self }
#[must_use]
pub fn sbwe(&mut self) -> SBWE_W<4> {
SBWE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand All @@ -194,11 +101,10 @@ impl crate::Readable for CLC_SPEC {
#[doc = "`write(|w| ..)` method takes [clc::W](W) writer structure"]
impl crate::Writable for CLC_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CLC to value 0x03"]
impl crate::Resettable for CLC_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0x03
}
const RESET_VALUE: Self::Ux = 0x03;
}

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