Skip to content

Commit

Permalink
Remove the form field from Mips16 instruction formats and set things
Browse files Browse the repository at this point in the history 
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information
Reed Kotler committed Feb 14, 2013
1 parent fd1335e commit 38f85c5
Show file tree
Hide file tree
Showing 3 changed files with 73 additions and 87 deletions.
14 changes: 14 additions & 0 deletions lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View file
Expand Up @@ -93,6 +93,11 @@ static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
Expand Down Expand Up @@ -322,6 +327,15 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
}

static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {

return MCDisassembler::Fail;

}

static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
Expand Down
111 changes: 37 additions & 74 deletions lib/Target/Mips/Mips16InstrFormats.td
View file
Expand Up @@ -29,45 +29,13 @@
//
//===----------------------------------------------------------------------===//

// Format specifies the encoding used by the instruction. This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
//
class Format16<bits<5> val> {
bits<5> Value = val;
}

def Pseudo16 : Format16<0>;
def FrmI16 : Format16<1>;
def FrmRI16 : Format16<2>;
def FrmRR16 : Format16<3>;
def FrmRRI16 : Format16<4>;
def FrmRRR16 : Format16<5>;
def FrmRRI_A16 : Format16<6>;
def FrmSHIFT16 : Format16<7>;
def FrmI8_TYPE16 : Format16<8>;
def FrmI8_MOVR3216 : Format16<9>;
def FrmI8_MOV32R16 : Format16<10>;
def FrmI8_SVRS16 : Format16<11>;
def FrmJAL16 : Format16<12>;
def FrmJALX16 : Format16<13>;
def FrmEXT_I16 : Format16<14>;
def FrmASMACRO16 : Format16<15>;
def FrmEXT_RI16 : Format16<16>;
def FrmEXT_RRI16 : Format16<17>;
def FrmEXT_RRI_A16 : Format16<18>;
def FrmEXT_SHIFT16 : Format16<19>;
def FrmEXT_I816 : Format16<20>;
def FrmEXT_I8_SVRS16 : Format16<21>;
def FrmOther16 : Format16<22>; // Instruction w/ a custom format

// Base class for Mips 16 Format
// This class does not depend on the instruction size
//
class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format16 f>: Instruction
InstrItinClass itin>: Instruction
{
Format16 Form = f;

let Namespace = "Mips";

Expand All @@ -78,45 +46,42 @@ class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
let Pattern = pattern;
let Itinerary = itin;

//
// Attributes specific to Mips instructions...
//
bits<5> FormBits = Form.Value;

// TSFlags layout should be kept in sync with MipsInstrInfo.h.
let TSFlags{4-0} = FormBits;

let Predicates = [InMips16Mode];
}

//
// Generic Mips 16 Format
//
class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format16 f>:
MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
InstrItinClass itin>:
MipsInst16_Base<outs, ins, asmstr, pattern, itin>
{
field bits<16> Inst;
bits<5> Opcode = 0;

// Top 5 bits are the 'opcode' field
let Inst{15-11} = Opcode;

let Size=2;
field bits<16> SoftFail = 0;
}

//
// For 32 bit extended instruction forms.
//
class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format16 f>:
MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
InstrItinClass itin>:
MipsInst16_Base<outs, ins, asmstr, pattern, itin>
{
field bits<32> Inst;


let Size=4;
field bits<32> SoftFail = 0;
}

class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format16 f>:
MipsInst16_32<outs, ins, asmstr, pattern, itin, f>
InstrItinClass itin>:
MipsInst16_32<outs, ins, asmstr, pattern, itin>
{
let Inst{31-27} = 0b11110;
}
Expand All @@ -125,7 +90,7 @@ class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,

// Mips Pseudo Instructions Format
class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}
Expand All @@ -137,7 +102,7 @@ class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:

class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmI16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<11> imm11;

Expand All @@ -152,7 +117,7 @@ class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,

class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<8> imm8;
Expand All @@ -169,7 +134,7 @@ class FRI16<bits<5> op, dag outs, dag ins, string asmstr,

class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<3> ry;
Expand All @@ -188,7 +153,7 @@ class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
//
class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
string asmstr, list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<3> subfunct;
Expand All @@ -208,7 +173,7 @@ class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
//
class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<6> _code; // code is a keyword in tablegen
bits<5> funct;
Expand All @@ -226,7 +191,7 @@ class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<1> nd;
Expand All @@ -252,7 +217,7 @@ class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,

class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<3> ry;
Expand All @@ -272,7 +237,7 @@ class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,

class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<3> ry;
Expand All @@ -294,7 +259,7 @@ class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,

class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<3> ry;
Expand All @@ -316,7 +281,7 @@ class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,

class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> rx;
bits<3> ry;
Expand All @@ -338,7 +303,7 @@ class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,

class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<3> func;
bits<8> imm8;
Expand All @@ -356,7 +321,7 @@ class FI816<bits<3> _func, dag outs, dag ins, string asmstr,

class FI8_MOVR3216<dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
MipsInst16<outs, ins, asmstr, pattern, itin>
{

bits<4> ry;
Expand All @@ -378,7 +343,7 @@ class FI8_MOVR3216<dag outs, dag ins, string asmstr,

class FI8_MOV32R16<dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{

bits<3> func;
Expand All @@ -402,7 +367,7 @@ class FI8_MOV32R16<dag outs, dag ins, string asmstr,

class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
MipsInst16<outs, ins, asmstr, pattern, itin>
{
bits<1> s;
bits<1> ra = 0;
Expand All @@ -429,7 +394,7 @@ class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,

class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
MipsInst16_32<outs, ins, asmstr, pattern, itin>
{
bits<1> X;
bits<26> imm26;
Expand All @@ -452,7 +417,7 @@ class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,

class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<16> imm16;
bits<5> eop;
Expand All @@ -474,7 +439,7 @@ class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,

class FASMACRO16<dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmASMACRO16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<3> select;
bits<3> p4;
Expand Down Expand Up @@ -503,7 +468,7 @@ class FASMACRO16<dag outs, dag ins, string asmstr,

class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RI16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<16> imm16;
bits<5> op;
Expand All @@ -527,7 +492,7 @@ class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,

class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<5> op;
bits<16> imm16;
Expand All @@ -552,7 +517,7 @@ class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,

class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI_A16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<15> imm15;
bits<3> rx;
Expand All @@ -578,7 +543,7 @@ class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,

class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_SHIFT16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<6> sa6;
bits<3> rx;
Expand All @@ -605,7 +570,7 @@ class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,

class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I816>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<16> imm16;
bits<5> I8;
Expand All @@ -630,7 +595,7 @@ class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,

class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
{
bits<3> xsregs =0;
bits<8> framesize =0;
Expand Down Expand Up @@ -659,5 +624,3 @@ class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,

}



0 comments on commit 38f85c5

Please sign in to comment.