[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.

This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8
yiannist · Mar 26, 2014 · 8e7aa4b · 8e7aa4b
1 parent 75203b6
commit 8e7aa4b
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Showing 5 changed files with 17 additions and 24 deletions.
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
@@ -363,36 +363,12 @@ def : InstAlias<"daddu $rs, $imm",
 def : InstAlias<"dadd $rs, $imm",
                 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
                 0>;
-def : InstAlias<"dadd $rs, $rt",
-                (DADD GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt),
-                0>;
-def : InstAlias<"daddu $rs, $rt",
-                (DADDu GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt),
-                0>;
-def : InstAlias<"dsub $rs, $rt",
-                (DSUB GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt),
-                0>;
-def : InstAlias<"dsubu $rs, $rt",
-                (DSUBu GPR64Opnd:$rs, GPR64Opnd:$rs, GPR64Opnd:$rt),
-                0>;
 def : InstAlias<"add $rs, $imm",
                 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
                 0>;
 def : InstAlias<"addu $rs, $imm",
                 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
                 0>;
-def : InstAlias<"add $rs, $rt",
-                (ADD GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt),
-                0>;
-def : InstAlias<"addu $rs, $rt",
-                (ADDu GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt),
-                0>;
-def : InstAlias<"sub $rs, $rt",
-                (SUB GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt),
-                0>;
-def : InstAlias<"subu $rs, $rt",
-                (SUBu GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt),
-                0>;
 let isPseudo=1, usesCustomInserter=1, isCodeGenOnly=1 in {
 def SUBi : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm),
                     "sub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
@@ -426,6 +426,7 @@ class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
          [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
   let isCommutable = isComm;
   let isReMaterializable = 1;
+  let TwoOperandAliasConstraint = "$rd = $rs";
 }
 
 // Arithmetic and logical instructions with 2 register operands.

diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
@@ -127,15 +127,23 @@
 # CHECK:	addu	$9, $9, $3	# encoding: [0x21,0x48,0x23,0x01]
 # CHECK:	addi	$9, $9, 10	# encoding: [0x0a,0x00,0x29,0x21]
 # CHECK:	addiu	$9, $9, 10	# encoding: [0x0a,0x00,0x29,0x25]
+# CHECK:	and	$5, $5, $6	# encoding: [0x24,0x28,0xa6,0x00]
+# CHECK:	mul	$9, $9, $3	# encoding: [0x02,0x48,0x23,0x71]
+# CHECK:	or	$2, $2, $4	# encoding: [0x25,0x10,0x44,0x00]
 # CHECK:	sub	$9, $9, $3	# encoding: [0x22,0x48,0x23,0x01]
 # CHECK:	subu	$9, $9, $3	# encoding: [0x23,0x48,0x23,0x01]
 # CHECK:	addi	$9, $9, -10	# encoding: [0xf6,0xff,0x29,0x21]
 # CHECK:	addiu	$9, $9, -10	# encoding: [0xf6,0xff,0x29,0x25]
+# CHECK:	xor	$9, $9, $10	# encoding: [0x26,0x48,0x2a,0x01]
 	add	$9, $3
 	addu	$9, $3
 	add	$9, 10
 	addu	$9, 10
+	and	$5, $6
+	mul	$9, $3
+	or	$2, $4
 	sub	$9, $3
 	subu	$9, $3
 	sub	$9, 10
 	subu	$9, 10
+	xor	$9, $10
diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s
@@ -116,6 +116,7 @@
 # Shortcuts for arithmetic instructions
 #------------------------------------------------------------------------------
 
+# CHECK:	and	$9, $9, $3	# encoding: [0x24,0x48,0x23,0x01]
 # CHECK:	dadd	$9, $9, $3	# encoding: [0x2c,0x48,0x23,0x01]
 # CHECK:	daddu	$9, $9, $3	# encoding: [0x2d,0x48,0x23,0x01]
 # CHECK:	daddi	$9, $9, 10	# encoding: [0x0a,0x00,0x29,0x61]
@@ -124,6 +125,9 @@
 # CHECK:	dsubu	$9, $9, $3	# encoding: [0x2f,0x48,0x23,0x01]
 # CHECK:	daddi	$9, $9, -10	# encoding: [0xf6,0xff,0x29,0x61]
 # CHECK:	daddiu	$9, $9, -10	# encoding: [0xf6,0xff,0x29,0x65]
+# CHECK:	or	$9, $9, $3	# encoding: [0x25,0x48,0x23,0x01]
+# CHECK:	xor	$9, $9, $3	# encoding: [0x26,0x48,0x23,0x01]
+	and	$9, $3
 	dadd	$9, $3
 	daddu	$9, $3
 	dadd	$9, 10
@@ -132,6 +136,8 @@
 	dsubu	$9, $3
 	dsub	$9, 10
 	dsubu	$9, 10
+	or	$9, $3
+	xor	$9, $3
 
 #------------------------------------------------------------------------------
 # Did you know that GAS supports complex arithmetic expressions in assembly?

diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s
@@ -2,6 +2,7 @@
 
 # CHECK: baddu $9, $6, $7             # encoding: [0x70,0xc7,0x48,0x28]
 # CHECK: baddu $17, $18, $19          # encoding: [0x72,0x53,0x88,0x28]
+# CHECK: dmul  $9, $9, $6             # encoding: [0x71,0x26,0x48,0x03]
 # CHECK: dmul  $9, $6, $7             # encoding: [0x70,0xc7,0x48,0x03]
 # CHECK: dmul  $19, $24, $25          # encoding: [0x73,0x19,0x98,0x03]
 # CHECK: dpop  $9, $6                 # encoding: [0x70,0xc0,0x48,0x2d]
@@ -13,6 +14,7 @@
 
   baddu $9, $6, $7
   baddu $17, $18, $19
+  dmul  $9, $6
   dmul  $9, $6, $7
   dmul  $19, $24, $25
   dpop  $9, $6