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SystemVerilog realization of RISC-V processor

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Name		Name	Last commit message	Last commit date
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design		design
doc		doc
sim		sim
syn		syn
verif		verif
.gitattributes		.gitattributes
LICENSE		LICENSE
README.md		README.md

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RISC-V-PipeLine

This is a SystemVerilog realization of RISC-V processor project Read doc/report.pdf to get more details

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SystemVerilog realization of RISC-V processor

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