Realization of Advance Lane Detection Algorithm on Xilinx ZYNQ-7000 using Vivado platform.
This project realized in verilog.
It is a sub-task of "REALIZATION OF LANE DETECTION ALGORITHMS ON FPGA USING SDSOC AND VIVADO" graduate project at Istanbul Technical University, June 2018.
Please visit main repository for more details:
1-) Main Repo -Full Project-: Lane Detection with implementation on FPGA
2-) C++ with OpenCV on just CPU without any acceleration with FPGA: Lane Detection on CPU Pure Software
3.1-) C++ with OpenCV on Arm processor and xfopencv on Hardware in Zynq-7000 series FPGA's, all steps of algorithms Lane Detection on FPGA-HW/SW part with SDSoC
3.2-) ✔️✔️ (This Repository) Verilog on hardware, only preprocess step: Lane Detection on FPGA-HW part with VIVADO
This project is a part of graduate project which is named as "REALIZATION OF LANE DETECTION ALGORITHMS ON FPGA USING SDSOC AND VIVADO" at Istanbul Technical University, June 2018.
Project members:
Yakup GÖRÜR (gorury@itu.edu.tr, yakup.gorur@gmail.com) - Software and SDSoC Platform
Mehmet Akif AKKAYA (akifakkaya1@gmail.com) - VIVADO Platform
Assoc. Prof. Dr. Sıddıka Berna ÖRS YALÇIN (Advisor)
** This project was supported by the Scientific and Technological Research Council of Turkey (TUBITAK).