fix lw

yttnn · Apr 5, 2024 · 46a3693 · 46a3693
1 parent 68a7b4f
commit 46a3693
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Showing 2 changed files with 28 additions and 7 deletions.
diff --git a/core/core.sv b/core/core.sv
@@ -134,6 +134,7 @@ module core (
                    (is_lui)            ? imm_u_sign_ext :
                    (is_auipc)          ? (pc + imm_u_sign_ext) :
                    (is_csr)            ? csr_rdata :
+                   (is_load)           ? load_data :
                    alu_out;
   assign wb_enable = (
     // state == EXECUTE &&
@@ -145,6 +146,7 @@ module core (
       is_jalr    ||
       is_lui     ||
       is_csr ||
+      is_load ||
       is_auipc
     )
   );
@@ -159,7 +161,8 @@ module core (
   // assign mem_addr = (state == WAIT_INSTR || state == FETCH) ? pc : load_store_addr;
   assign mem_addr = load_store_addr;
   assign rom_addr = pc;
-  assign mem_r_enable = (state == FETCH || (state == MEM_ACCESS && is_load));
+  // assign mem_r_enable = (state == FETCH || (state == MEM_ACCESS && is_load));
+  assign mem_r_enable = (state == MEM_ACCESS && is_load);
   assign mem_w_enable = ((state == MEM_ACCESS) && is_store);
 
   always @(posedge clk ) begin
@@ -227,9 +230,14 @@ module core (
           if (wb_enable && rd != 0) begin
             registers[rd] <= wb_data;
             `ifdef DEBUG
-            // $display("x[%0d] <= %b", rd, wb_data);
+            if (is_load) begin
+            $display("mem[%h]=%h", load_store_addr, load_data);
+            $display("wbdata=%h", wb_data);
+            end
             `endif
           end
+          // $display("mem[%h]=%h", load_store_addr, load_data);
+          // $display("wbdata=%h", wb_data);
           pc <= next_pc;
           state <= FETCH;
         end
@@ -247,14 +255,14 @@ module core (
   always @(posedge clk) begin
     if (state == DECODE) begin
     // $display("PC=%0d", pc);
-    // $display("pc=%h, gp=%d, t5=%d, t6=%d, mcause=%h", pc, registers[3], registers[30], registers[31], csr_regs[12'h342]);
+    $display("pc=%h, gp=%d, ra=%h, sp=%h, a4=%h, a5=%h, t2=%h", pc, registers[3], registers[1], registers[2], registers[14], registers[15], registers[7]);
     case (1'b1)
       is_alu_reg : $display("alu_reg rd=%d, rs1=%d, rs2=%d, funct3=%b", rd, rs1_addr, rs2_addr, funct3);
       is_alu_imm : $display("alu_imm rd=%d, rs1=%d, imm=%d, funct3=%b", rd, rs1_addr, rs2_addr, funct3);
       is_branch  : $display("branch rs1=%0d rs2=%0d", rs1_addr, rs2_addr);
       is_jal     : $display("jal");
       is_jalr    : $display("jalr");
-      is_auipc   : $display("auipc %d", imm_u_sign_ext);
+      is_auipc   : $display("auipc %h", imm_u_sign_ext);
       is_lui     : $display("lui");
       is_load    : $display("load");
       is_store   : $display("store");

diff --git a/core/memory.sv b/core/memory.sv
@@ -10,10 +10,23 @@ module memory (
   output logic [31:0] mem_rdata
 );
 
-  logic [31:0] MEM [0:255];
+  logic [31:0] MEM [0:4095];
   // localparam start = 32'h00000000;
   logic [7:0] ROM [0: 16384];
+  integer i;
   initial begin
+    for (i = 0; i<4096; i++) begin
+      MEM[i] = 32'h0;
+    end
+    // MEM[0] = {32'h22222222};
+    // ROM[0] = {8'h03};
+    // ROM[1] = {8'h23};
+    // ROM[2] = {8'h00};
+    // ROM[3] = {8'h00};
+    // ROM[4] = {8'h11};
+    // ROM[5] = {8'h12};
+    // ROM[6] = {8'h13};
+    // ROM[7] = {8'h14};
     // $readmemh("../riscv-tests/hex/rv32ui-p-add.hex", ROM);
     // $readmemh("../riscv-tests/hex/rv32ui-p-addi.hex", ROM);
     // $readmemh("../riscv-tests/hex/rv32ui-p-and.hex", ROM);
@@ -51,9 +64,9 @@ module memory (
     // $readmemh("../riscv-tests/hex/rv32ui-p-srl.hex", ROM);
     // $readmemh("../riscv-tests/hex/rv32ui-p-srli.hex", ROM);
     // $readmemh("../riscv-tests/hex/rv32ui-p-sub.hex", ROM);
-    // $readmemh("../riscv-tests/hex/rv32ui-p-sw.hex", ROM);
+    $readmemh("../riscv-tests/hex/rv32ui-p-sw.hex", ROM);
     // $readmemh("../riscv-tests/hex/rv32ui-p-xor.hex", ROM);
-    $readmemh("../riscv-tests/hex/rv32ui-p-xori.hex", ROM);
+    // $readmemh("../riscv-tests/hex/rv32ui-p-xori.hex", ROM);
   end
 
   `include "riscv_assembly.v"